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Filtering by: Creator Osborn, T. R. Remove constraint Creator: Osborn, T. R. Committee Member Nguyen, Thinh Remove constraint Committee Member: Nguyen, Thinh Subject Cache memory Remove constraint Subject: Cache memory

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  • Single-level dynamic register caching architecture for high-performance superscalar processors

    Creator:
    Liebert, John A.
    Abstract:
    The amount of instruction level parallelism (ILP) that can be exploited depends greatly on the size of the instruction window and the number of in-flight instructions the processor can support. However, this requires a register file with a large set of physical registers for renaming and multiple ports to provide...
    Resource Type:
    Masters Thesis
    Full Text:
    R e la ti v e I P C I m p ro v e m e n t 4Cache / 12Full 6Cache / 10Full 8Cache / 8Full

  • Asymmetric clustering using a register cache

    Creator:
    Morrison, Roger Allen
    Abstract:
    Conventional register files spread porting resources uniformly across all registers. This paper proposes a method called Asymmetric Clustering using a Register Cache (ACRC). ACRC utilizes a fast register cache that concentrates valuable register file ports to the most active registers thereby reducing the total register file area and power consumption....
    Resource Type:
    Masters Thesis
    Full Text:
    the rename and issue stages are shown in Figure 3. The rename stage contains an array of ‘ready’ (R

  • Power reduction of MPEG video decoding for mobile multimedia systems

    Creator:
    Lewis, James M.
    Abstract:
    The purpose of this thesis is to explore methods which can reduce the power dissipation of a mobile system while decoding MPEG video. MPEG decoding is a microprocessor intensive process that makes heavy use of both the L1 and L2 caches as well as main memory. The heavy load placed...
    Resource Type:
    Masters Thesis