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  • Design techniques for delta sigma modulators using VCO based ADCs

    Creator:
    Reddy, Karthikeyan
    Abstract:
    VCO-based ADCs have recently emerged as attractive alternative to conventional DeltaSigma (ΔΣ) modulator architectures. Few salient features of a VCObased ADC are: 1) the quantization noise is 1st order noise shaped, 2) it is an open loop architecture, and, 3) its implementation is mostly digital in nature. Hence, they are...
    Resource Type:
    Dissertation
    Full Text:
    NTF and NTF of the real modulator after matching for p=Fs and τ = 0.5

  • Time and statistical information utilization in high efficiency sub-micron CMOS successive approximation analog to digital converters

    Creator:
    Guerber, Jon
    Abstract:
    In an industrial and consumer electronic marketplace that is increasingly demanding greater real-world interactivity in portable and distributed devices, analog to digital converter efficiency and performance is being carefully examined. The successive approximation (SAR) analog to digital converter (ADC) architecture has become popular for its high efficiency at mid-speed and...
    Resource Type:
    Dissertation
    Full Text:
    ................................................................... 69 Figure 3.36: TSAR die photo along with calibration and full-chip views

  • Design techniques for low-power multi-GS/s analog-to-digital converters

    Creator:
    Jiang, Tao
    Abstract:
    Ultra-high-speed (>10GS/s), medium-resolution (5~6bit), low-power (<50mW) analog-to-digital converter can find it application in the areas of digital oscilloscopes and next-generation serial link receivers. There are several challenges to enable a successful design, however. First, the time-interleaved architecture is required in order to achieve over 10GS/s sampling rate, with the trade-off...
    Resource Type:
    Dissertation
    Full Text:
    ............................................................................. 69 Measurement Results

  • Efficient use of time information in analog-to-digital converters

    Creator:
    Hu, Yue
    Abstract:
    Time-domain data conversion has recently drawn increased research attention for its highly digital nature in favor of process technology scaling. Also, as the time information being carried by binary voltage, time-domain operation is much less sensitive to voltage noise compared to conventional voltage domain operation. However, for analog-to-digital converter (ADC)...
    Resource Type:
    Dissertation
    Full Text:
    Figure 3.35: Measured output spectrum with -3dBFS signal at 210kHz. .................... 69 (Frequency

  • Digital Friendly Continuous-Time Delta-Sigma Analog-to-Digital Converters

    Creator:
    Maghami, Hamidreza
    Abstract:
    Conventional Delta-Sigma analog-to-digital converters (ADCs) utilize operational transconductance amplifiers (OTAs) in their loop filter implementation followed by multi-bit voltage domain quantizers. As CMOS integrated circuit technology scales to smaller geometries, the minimum transistor length and the intrinsic gain of the transistors decrease. Moreover, with process scaling the voltage headroom decreases...
    Resource Type:
    Dissertation
    Full Text:
    . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 3.2 Architectural level analysis of OTA-less 1-1 MASH VCO-based ADC 72 3.2.1 Open loop first

  • Low-power design techniques for low-voltage analog-to-digital converters

    Creator:
    Kim, Min Gyu
    Abstract:
    The demand for portable electronic systems and the continued down-scaling of device dimensions resulted in rapid improvement in the performance of integrated systems. Several low-voltage design techniques have been proposed to operate analog circuits with sub-1V supply. However, these techniques require higher power consumption to achieve large dynamic range while...
    Resource Type:
    Dissertation
    Full Text:
    . The factor OSR is referred to as the oversampling ratio (OSR), OSR = fs/2fB. Fig. 3.3 (a) and (b) are

  • Design techniques for low-voltage and low-power analog-to-digital converters

    Creator:
    Ahn, Gil Cho
    Abstract:
    With the ever-increasing demand for portable devices used in applications such as wireless communication, mobile computing, consumer electronics, etc., the scaling of the CMOS process to deep submicron dimensions becomes more important to achieve low-cost, low-power and high-performance digital systems. However, this downscaling also requires similar shrinking of the supply...
    Resource Type:
    Dissertation
    Full Text:
    6.1 Performance summary of the prototype pipelined ADC.. . . . . . . . . . 69 To my parents Haesook

  • Ring amplification for switched capacitor circuits

    Creator:
    Hershberg, Benjamin Poris
    Abstract:
    A comprehensive and scalable solution for high-performance switched capacitor amplification is presented. Central to this discussion is the concept of ring amplification. A ring amplifier is a small modular amplifier derived from a ring oscillator that naturally embodies all the essential elements of scalability. It can amplify with accurate rail-to-rail...
    Resource Type:
    Dissertation
    Full Text:
    . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.4.2 Implementation Details

  • Power-Efficient Design Techniques and Architectures for Scalable Submicron Analog Circuits

    Creator:
    Xu, Yang
    Abstract:
    As the CMOS process scales down to submicron, digital circuit performance improves, while reduced supply voltage and lower transistor intrinsic gain make it difficult to implement analog circuits in a power efficient manner. Therefore, it has become advantageous to shift more analog signal processing functions conventionally realized in voltage (analog)...
    Resource Type:
    Dissertation
    Full Text:
    Circuit Implementation ……………………………………………..…….. 68 4.4.1 ΔΣ Modulator …………………………………………….………. 69 4.4.2

  • A comparative study between sinusoidal and squarewave clocking for alleviating the jitter limitation in multi-gigaHertz ADCs

    Creator:
    Kesharwani, Divya
    Abstract:
    Various applications like wireless UWB communication, fast data acquisition systems and digital storage oscilloscopes needs ADCs with instantaneous input signal bandwidth from 0.1-40 GigaHertz range with 6-10 bits of resolution -- a challenging task and an impressive goal to achieve. Flash ADCs have been conventionally employed to achieve these goals...
    Resource Type:
    Masters Thesis
    Full Text:
    -sampled at fs, with a series of n T/Hs circuits (T/H1, T/H2, . . ., T/Hn) using phase shifted clocks (CK1