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Filtering by: Creator Chen, Jiaming Remove constraint Creator: Chen, Jiaming Creator Meng, Xin Remove constraint Creator: Meng, Xin Subject Analog-to-digital converters -- Design and construction Remove constraint Subject: Analog-to-digital converters -- Design and construction

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  • Wideband discrete-time delta-sigma analog-to-digital converters with shifted loop delays

    Creator:
    Meng, Xin
    Abstract:
    Low-distortion architecture is widely used in wideband discrete-time switched-capacitor delta-sigma ADC design. However, it suffers from the power-hungry active adder and critical timing for quantization and dynamic element matching (DEM). To solve this problem, this dissertation presents a delta-sigma modulator architecture with shifted loop delays. In this project, shifted loop...
    Resource Type:
    Dissertation
    Full Text:
    , Weilun Shen, Yan Wang, Jiaming Lin, Jeongseok Chae, Sanghyeon Lee, Youngho Jung, Pedram Payandehnia