A low-power forwarded-clock I/O transceiver architecture is presented that employs a high degree of output/input multiplexing, supply-voltage scaling with data rate, and low-voltage circuit techniques to enable low-power operation. The transmitter utilizes a 4:1 output multiplexing voltage-mode driver along with 4-phase clocking that is efficiently generated from a passive poly-phase...
A statistical analysis technique for estimating bit-error rate (BER) and eye
opening is presented for both NRZ and duobinary signaling schemes. This method
enables fast and accurate BER distribution simulation of a serial link transceiver
including channel and circuit imperfections, such as finite pulse rise/fall time, duty cycle
variation, and...
High speed serial links are critical components for addressing the growing demand for I/O bandwidth in next-generation computing applications, such as many-core systems, backplane and optical data communications. Due to continued process scaling and circuit innovations, today's CMOS serial link transceivers can achieve tens of Gb/s per pin. However, most...