Index Catalog // ScholarsArchive@OSU

Equalizer design for MDFE channels using nonlinear optimization

Creator:: Onu, Dan
Abstract:: Decision feedback equalization (DFE) is a sampled-data technique used for data recovery in digital communications channels. Multi-level decision feedback equalization (MDFE) has been developed for channels using the 2/3(1,7) RLL code. The optimum detector for a digital communication channel affected by ISI and noise consists of a matched filter, followed...
Resource Type:: Masters Thesis
Full Text:: the APF, and the type and corner frequency of the LPF. A symbolic approach to the equalizer design

Design of high-speed low-power analog CMOS decision feedback equalizers

Creator:: Su, Wenjun
Abstract:: Decision feedback equalizer (DFE) is an effective method to remove inter-symbol interference (ISI) from a disk-drive read channel. Analog IC implementations of DFE potentially offers higher speed, smaller die area, and lower power consumption when compared to their digital counterparts. Most of the available DFE equalizers were realized by using...
Resource Type:: Masters Thesis
Full Text:: of Science in Electrical and Computer Engineerin presented on July 8th. 1996. Title: Design Of High

Design of high-speed adaptive parallel multi-level decision feedback equalizer

Creator:: Xiang, Yihai
Abstract:: Multi-level decision feedback equalization (MDFE) is an effective technique to remove inter-symbol interference (ISI) from disk readback signals, which uses the simple architecture of decision feedback equalization. Parallelism which doubles the symbol rate can be realized by setting the first tap of the feedback filter to zero. A mixed-signal implementation...
Resource Type:: Masters Thesis
Full Text:: Electrical and Computer Engineering presented on Feb. 26th, 1997. Title: Design of High-Speed Adaptive

Switched-current logic for digital circuit design

Creator:: Subramanian, Vivek
Resource Type:: Masters Thesis
Full Text:: design is introduced and is called Switched-Current (SI) Logic. This concept enhances high-performance

Improved design techniques for low-voltage low-power switched-capacitor delta-sigma modulators

Creator:: Grilo, Jorge
Abstract:: This dissertation investigates the constraints which arise when switched-capacitor (SC) delta-sigma modulators are designed for low-voltage operation, targeting also low power dissipation, and proposes methods of improving the performance and optimizing for low power dissipation. This is accomplished by identifying critical elements whose performance can lead to increased power dissipation,...
Resource Type:: Dissertation
Full Text:: Philosophy in Electrical and Computer Engineering presented on June 27, 1997. Title: Improved Design

CounterDataFlow architecture : design and performance

Creator:: Miller, Michael F., (Michael Frederic)
Abstract:: The counterflow pipeline concept was originated by Sproull and Sutherland to demonstrate the concept of asynchronous circuits. This architecture relies on distributed decision making and localized clocking and data movement. We have taken these ideas and reformulated them into a substantially faster more scalable architecture that has the same distributed...
Resource Type:: Masters Thesis

Design of switched-current circuits for a bandpass delta-sigma modulator

Creator:: Manapragada, Praveen
Resource Type:: Masters Thesis
Full Text:: a switched-current bandpass delta-sigma modulator. This thesis presents the design and layout of a

Resonant forward-biased guard rings for suppression of substrate noise in mixed-mode CMOS circuits

Creator:: Ficq, Bernard L.
Abstract:: Previous work at Stanford University has demonstrated that inductance in the substrate connection is the principal problem underlying the coupling of digital switching noise into analog circuits. The low impedance substrate can be treated as a single node over a local area. Switching in the digital circuits produces current transients...
Resource Type:: Masters Thesis
Full Text:: . 370-379, Apr. 1989. [3] L.A. Glasser and D.W. Dobberpuhl, The Design and Analysis of VLSI Circuits

Design of high-speed summing circuitry and comparator for adaptive parallel multi-level decision feedback equalization

Creator:: Gao, Hairong
Abstract:: Multi-level decision feedback equalization (MDFE) is an effective sampled signal processing technique to remove inter-symbol interference (ISI) from disk read-back signals. Parallelism which doubles the symbol rate can be realized by utilizing the characteristic of channel response and decision feedback equalization algorithm. A mixed-signal IC implementation has been chosen for...
Resource Type:: Masters Thesis
Full Text:: Design of high-speed summing circuitry and comparator for

Loadmaster : weight-based kiln control

Creator:: Laurenzi, Tom, Greene, Ed, Western Dry Kiln Association, and Western Dry Kiln Association. Meeting (47th : 1996 : Vancouver, B.C.)
Resource Type:: Conference Proceeding
Full Text:: technology at the University of Tennessee, collaborated to research and design a weight-based dry kiln

ScholarsArchive@OSU

Equalizer design for MDFE channels using nonlinear optimization

Design of high-speed low-power analog CMOS decision feedback equalizers

Design of high-speed adaptive parallel multi-level decision feedback equalizer

Switched-current logic for digital circuit design

Improved design techniques for low-voltage low-power switched-capacitor delta-sigma modulators

CounterDataFlow architecture : design and performance

Design of switched-current circuits for a bandpass delta-sigma modulator

Resonant forward-biased guard rings for suppression of substrate noise in mixed-mode CMOS circuits

Design of high-speed summing circuitry and comparator for adaptive parallel multi-level decision feedback equalization

Loadmaster : weight-based kiln control

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