Oversampled data converters are becoming increasingly popular
for high-precision data conversion. There have been many
publications on oversampled analog-to-digital (A/D) converters but
relatively few on oversampled digital-to-analog (D/A) converters.
In this thesis, issues concerning the analysis and design of the
oversampled D/A converters are addressed. Simulation tools and
analytical methods...
High-accuracy and high-speed CMOS track-and-hold (T/H) or sample-and-hold (S/H) circuits are an important part of the analog-to-digital interface. The switched-capacitor (SC) circuits usually contain one or more op-amps whose dc offset, finite gain, finite bandwidth have a big impact on the accuracy of the track-and-hold circuit. Basic correlated double sampling...
Oversampling and noise-shaping methods for digital-to-analog (D/A) conversion have
been widely accepted as methods of choice in high performance data conversion
applications. In this thesis, the fundamentals of D/A conversion and oversampling D/A
conversion were discussed, along with the detailed analysis and comparison of the reported
state-of-the-art oversampling D/A converters....
This thesis describes design techniques for high-performance switched-capacitor
(SC) circuits, primarily for high-linearity low-noise SC circuits in the presence of
component imperfections, such as nonlinear op-amp voltage transfer characteristics,
capacitor nonlinearities as well as the finite op-amp dc gain and op-amp offset and noise.
Various correlated-double-sampling (CDS) schemes are discussed,...
This dissertation investigates the constraints which arise when switched-capacitor
(SC) delta-sigma modulators are designed for low-voltage operation, targeting also low
power dissipation, and proposes methods of improving the performance and optimizing
for low power dissipation. This is accomplished by identifying critical elements whose
performance can lead to increased power dissipation,...
It has been verified by theoretical analysis, circuit simulation and test that two
switch transistors in parallel in a simple sample and hold circuit can be achieve high speed
with low error voltage due to charge injection. The wide transistor provides low RC time
constant when it is closed and...
In this thesis, novel design techniques have been proposed for implementing high-linearity SC circuits in a standard digital CMOS process. They use nonlinear MOSFET capacitors instead of linear double-poly capacitors. To reduce their nonlinearities, a bias voltage is applied to keep MOSFET capacitors in their accumulation regions. For further reduction...
This thesis describes compensation techniques for cascaded delta-sigma A/D
converters (ADCs) and high-performance switched-capacitor (SC) circuits. Various
correlated-double-sampling (CDS) techniques are presented to reduce the effects of the
nonidealities, such as clock feedthrough, charge injection, opamp input-referred noise and
offset, and finite opamp gain, in SC circuits. A CDS technique...