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Filtering by: Subject Embedded computer systems -- Testing Remove constraint Subject: Embedded computer systems -- Testing Decade 2010-2019 Remove constraint Decade: 2010-2019

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  • Optimizing performance/watt of embedded SIMD multiprocessors through a priori application guided power scheduling

    Creator:
    Albright, Ryan K.
    Abstract:
    A method for improving performance/watt of an embedded single-instruction multiple-data (SIMD) architecture using application-guided a priori scheduling of hardware resources is presented. A multi-core architectural simulator is adopted that accurately estimates power, performance, and utilization of various processor components (logic, interconnect and memory). A greedy search is then performed on...
    Resource Type:
    Masters Thesis
    Full Text:
    Developement Flow First, we model an embedded multi-core system using a simulator based on the MV5 framework

  • Leveraging Generated Tests

    Creator:
    Alipour, Mohammad Amin
    Abstract:
    The main goal of automated test generation is to improve the reliability of a program by exposing faults to developers. To this end, testing should cover the largest possible portion of the program given a test budget (i.e., time and resources) as frequently as possible. Coverage of a program entity...
    Resource Type:
    Dissertation
    Full Text:
    testing has little ability (without considerable human effort) to focus on part of a system under test

  • Simulator for optimizing performance and power of embedded multicore processors

    Creator:
    Goska, Benjamin J.
    Abstract:
    This work presents improvements to a multi-core performance/power simulator. The improvements which include updated power models, voltage scaling aware models, and an application specific benchmark, are done to increase the accuracy of power models under voltage and frequency scaling. Improvements to the simulator enable more accurate design space exploration for...
    Resource Type:
    Masters Thesis
    Full Text:
    degree of Master of Science in Electrical and Computer Engineering presented on April 26, 2012. Title

  • The Architecture of a Reusable Built-In Self-Test for Link Training, IO and Memory Defect Detection and Auto Repair on 14nm Intel SOC

    Creator:
    Querbach, Bruce
    Abstract:
    The complexity of designing and testing today's system on chip (SOC) is increasing due to greater integrated circuit (IC) density and higher IO and memory frequencies. SOCs for the mobile phone and tablet market have the unique challenge of short product development windows, at times less than six months, and...
    Resource Type:
    Dissertation
    Full Text:
    : ______________________________________________________ Patrick Y. Chiang The complexity of designing and testing today’s system on chip