This thesis describes the analysis and comparison of Folded Source-Coupled
Logic (FSCL) with standard static CMOS, cascode voltage-switch logic and differential
split-level logic gates. The advantages of FSCL are low switching noise and
high operating speed. The effect of voltage and device scaling on these topologies is
evaluated in terms...
Previous work at Stanford University has demonstrated that inductance in the
substrate connection is the principal problem underlying the coupling of digital
switching noise into analog circuits. The low impedance substrate can be treated
as a single node over a local area. Switching in the digital circuits produces
current transients...
A CMOS implementation of a True-Q Flip Flop is presented. It can perform either as
an asynchronous storage element in micropipelines or a part of the synchronizer. It is
capable of double-edge triggering which latches data at both the rising and the trailing
edges. It is also free of the...