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  • CMOS differential logic techniques for mixed-mode applications

    Creator:
    Chee, San-hwa
    Resource Type:
    Masters Thesis
    Full Text:
    Test structure for the characterization of FS CL inverter 39 26 Power-Delay characteristic of FSCL

  • Influence of adjustable speed drive on induction motor fault detection using stator current monitoring.

    Creator:
    Al-Shahrani, Ali
    Abstract:
    The detection of motor faults at their incipient stage is of prime importance to any industrial plant. The introduction of adjustable speed drives has improved the control and the efficiency of induction motors, however, this has changed the nature of motor faults and how they can be detected. Current signature...
    Resource Type:
    Masters Thesis
    Full Text:
    ) Page 5.2.2.2 Dynamic eccentricity severity test……………………...58 5.2.2.3 Negative and positive

  • Experimental verification of a mismatch-shaping DAC

    Creator:
    Hudson, William Forrest, 1971-
    Abstract:
    Delta-sigma data converters have gained popularity in both analog-to-digital and digital-to-analog converters (ADCs and DACs) due to their simplicity, high linearity and immunity to many analog circuit imperfections. These data converters include features such as oversampling, noise-shaping, and (historically) single-bit quantization. Single-bit converters are preferred for their inherent linearity. This...
    Resource Type:
    Masters Thesis
    Full Text:
    equipment. 40 4.8 Output spectrum with fs = 500 kHz, 0th order ESL. 41 4.9 Output spectrum with fs = 500

  • Detection of incipient rotor bar faults and air-gap asymmetries in squirrel-cage motors using stator current monitoring

    Creator:
    Al Tuaimi, Hamad A.
    Abstract:
    Preventative motor fault detection is of prime importance for modern plant management. During research into rotor faults, performed at the Motor Systems Resource Facility (MSRF), an optimized rotor fault detection and classification method was proposed. In critical process applications, the suggested method would provide the foundation for continually monitoring a...
    Resource Type:
    Masters Thesis
    Full Text:
    sideband at (is-fr) (b) Eccentricity sideband at (is+ fr) ( c) Eccentricity sideband at (fs-2/r) ( d

  • Time domain characterization of interconnect discontinuities

    Creator:
    Jong, Jyh-Ming
    Abstract:
    The purpose of this study is to develop experimental techniques to characterize typical interconnect discontinuities, including bends, steps, T junctions, vias and pads, which are the most commonly encountered interconnections in high speed digital integrated circuits, hybrid and monolithic microwave circuits and electronic packages. The time domain reflection response of...
    Resource Type:
    Masters Thesis
    Full Text:
    Reflection voltage due to a pad with different impedance ratio 58 18 Test fixture used for characterizing a

  • Lowpass and bandpass current-mode delta-sigma DACs employing mismatch-shaping

    Creator:
    Shui, Tao, 1969-
    Abstract:
    Delta-sigma modulators are currently a very popular technique for making high-resolution analog-to-digital converters (ADCs) and digital-to-analog converters (DACs). These oversampled data converters have several advantages over conventional Nyquist-rate converters, including an insensitivity to many analog component imperfections, a simpler antialiasing filter and reduced accuracy requirements in the sample and hold....
    Resource Type:
    Dissertation
    Full Text:
    ) shaping. 58 4.7: Measured HD2 vs. sampling frequency for UEDAC1 59 4.8: Simulated spectra with measured

  • Comparison of DPCM and Subband Codec performance in the presence of burst errors

    Creator:
    Bhutani, Meeta
    Abstract:
    This thesis is a preliminary study of the relative performance of the major speech compression techniques, Differential Pulse Code Modulation (DPCM) and Subband Coding (SBC) in the presence of transmission distortion. The combined effect of the channel distortions and the channel codec including error correction is represented by bursts of...
    Resource Type:
    Masters Thesis
    Full Text:
    Introduction 57 3.2 Overall Picture 58 3.3 The Burst Error Channel 58 TABLE OF CONTENTS (Continued

  • Analysis and design of bandpass delta-sigma A/D converters

    Creator:
    Zhai, Dalun
    Abstract:
    A new approach to oversampled delta-sigma A/D converters ( AZ modulators ) is introduced, where a differential pseudo-Npath filter stage is used as a basic cell. In this band-pass application, the z to -zN transformation is employed to realize a RAM-type pseudo-2-path lossless integrator. The bandpass second-order and 4th-order delta-sigma...
    Resource Type:
    Masters Thesis
    Full Text:
    sampling rate to Nyquist rate: OSR=fs I 2fb (1) Fig.1 shows the output waveform difference between a

  • Novel switched-capacitor circuits for delta-sigma modulators

    Creator:
    Yesilyurt, Ayse Gul
    Abstract:
    Oversampled delta-sigma modulation is one of the widely used A/D conversion techniques for narrow bandwidth signals. In this study several new lowpass and bandpass delta-sigma modulator architectures as well as novel pseudo-N-path integrators that can be used in implementing these architectures are proposed. By using multiplexing techniques the new lowpass...
    Resource Type:
    Dissertation
    Full Text:
    ) 57 4.12. (a) Simulated gain responses of the SC filter with the integrator in Fig. 4.6 58 (b

  • Digital clocks based upon dual side band suppressed carrier modulation

    Creator:
    Arnett, David W.
    Abstract:
    A method and apparatus are presented for generating suppressed carrier digital clock signals. These clock signals have the advantage of being broad band in nature and thus exhibiting lower power spectral density. Structures or systems utilizing such clock signals would be less likely to create electromagnetic noise of sufficient intensity...
    Resource Type:
    Masters Thesis
    Full Text:
    6.10 33.33 MHz Clock with 8.3 MHz Square Wave Modulation. 58 62 6.11 Modulated 33.33 MHz Clock