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Filtering by: Subject Memory Remove constraint Subject: Memory Degree Field Electrical and Computer Engineering Remove constraint Degree Field: Electrical and Computer Engineering Subject Cache memory Remove constraint Subject: Cache memory

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  • Processor memory traffic characteristics for on-chip cache

    Creator:
    Ho, Jeremy Yui Luen
    Abstract:
    The motivation of this research is to study different cache designs for on-chip caches that improve processor performance and at the same time minimize the degradation to system performance caused by an increase in the processor memory traffic. As VLSI technology advances we can have bigger and more complex on-chip...
    Resource Type:
    Masters Thesis
    Full Text:
    Processor memory traffic characteristics for on-chip

  • Asymmetric clustering using a register cache

    Creator:
    Morrison, Roger Allen
    Abstract:
    Conventional register files spread porting resources uniformly across all registers. This paper proposes a method called Asymmetric Clustering using a Register Cache (ACRC). ACRC utilizes a fast register cache that concentrates valuable register file ports to the most active registers thereby reducing the total register file area and power consumption....
    Resource Type:
    Masters Thesis
    Full Text:
    ROB and Ld/St queue Issue queue size L1 I and D-cache L2 unified cache TLB Memory

  • A token caching waiting-matching unit for tagged-token dataflow computers

    Creator:
    Traylor, Roger L.
    Abstract:
    Computers using the tagged-token dataflow model are among the best candidates for delivering extremely high levels of performance required in the future. Instruction scheduling in these computers is determined by associatively matching data-bearing tokens in a Waiting-Matching Unit (W-M unit). At the W-M unit, incoming tokens with matching contexts are...
    Resource Type:
    Masters Thesis
    Full Text:
    caching technique. Using a recently developed CAM memory structure as a base, a token caching scheme is

  • Single-level dynamic register caching architecture for high-performance superscalar processors

    Creator:
    Liebert, John A.
    Abstract:
    The amount of instruction level parallelism (ILP) that can be exploited depends greatly on the size of the instruction window and the number of in-flight instructions the processor can support. However, this requires a register file with a large set of physical registers for renaming and multiple ports to provide...
    Resource Type:
    Masters Thesis
    Full Text:
    [18, 15]. This scheme works similar to a traditional multi-level cache memory, where a small, fully

  • Power reduction of MPEG video decoding for mobile multimedia systems

    Creator:
    Lewis, James M.
    Abstract:
    The purpose of this thesis is to explore methods which can reduce the power dissipation of a mobile system while decoding MPEG video. MPEG decoding is a microprocessor intensive process that makes heavy use of both the L1 and L2 caches as well as main memory. The heavy load placed...
    Resource Type:
    Masters Thesis
    Full Text:
    process that makes heavy use of both the L1 and L2 caches as well as main memory. The heavy load placed