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Filtering by: Creator Su, X. Remove constraint Creator: Su, X. Degree Field Electrical and Computer Engineering Remove constraint Degree Field: Electrical and Computer Engineering Subject Substrate noise Remove constraint Subject: Substrate noise

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  • Resonant forward-biased guard rings for suppression of substrate noise in mixed-mode CMOS circuits

    Creator:
    Ficq, Bernard L.
    Abstract:
    Previous work at Stanford University has demonstrated that inductance in the substrate connection is the principal problem underlying the coupling of digital switching noise into analog circuits. The low impedance substrate can be treated as a single node over a local area. Switching in the digital circuits produces current transients...
    Resource Type:
    Masters Thesis
    Full Text:
    pins were suggested by Su et al. [1] to reduce the effects of switching noise. Su et al. also

  • A substrate noise coupling model for lightly doped CMOS processes

    Creator:
    Sadate, Aline C.
    Abstract:
    This thesis presents a design-oriented model for lightly doped CMOS substrates. The model predicts the substrate noise coupling between noisy digital and sensitive analog blocks in the early stages of the design. The model scales with the size and separation of these blocks and it is validated with device simulations...
    Resource Type:
    Masters Thesis
    Full Text:
    sepa- rations between the injector and the sensor: (a) 10µm and (b) 100µm. 5 ... 6 x Backplane

  • Suppression of substrate noise in a mixed-signal CMOS integrated circuit

    Creator:
    Lim, Wei Tjan (Richard)
    Abstract:
    Substrate switching noise is becoming a concern as integrated circuits get larger and speeds get faster. Mixed-mode integrated circuits are especially affected as the substrate noise interferes with sensitive analog circuits resulting in limited signal to noise ratios. This thesis serves to study the cause of the noise at the...
    Resource Type:
    Masters Thesis
    Full Text:
    substrate. Figure 2.2 is the cross-section profile of the integrated circuit. Su et.al [5] found that

  • Test fixture characterization for high-frequency silicon substrate parasitic extraction

    Creator:
    Tabalujan, Andrew R.
    Abstract:
    At frequencies exceeding 1-2 GHz, the reactive nature of a silicon substrate must be accounted in the substrate network models used in substrate coupling simulation. High-frequency substrate models, containing reactive components, must be validated through high-frequency network analyzer measurements. Prior fabricated test fixtures have been modified to enable high-frequency (up...
    Resource Type:
    Masters Thesis
    Full Text:
    fixtures for (a) on-chip through trace, (b) on-chip empty contacts, (c) 10µm x 10µm contact, and (d) 10µm x

  • Ground tap placement and sizing to minimize substrate noise coupling in RF LNAs

    Creator:
    Sundaresan, Arathi
    Abstract:
    The substrate noise injected by a stepped buffer circuit into two single-ended 1.5GHz low noise amplifiers is examined for a heavily doped 0.25µm CMOS process. The difference in the LNA noise rejection is characterized as a function of the size and placement of substrate contacts. The use of a resistive...
    Resource Type:
    Masters Thesis
    Full Text:
    ..................................................................... 32 5.11 Simulated noise levels for substrate contact areas scaled from X to 6,400X. ... 34 5.12

  • Substrate noise coupling in ring oscillator-based phase locked loops

    Creator:
    Shreeve, Robert
    Abstract:
    In this thesis, the performance degradation of a phase-locked loop due to substrate noise is examined. A new analytical equivalent circuit model for substrate noise coupling is derived for a heavily doped silicon substrate. The model has been validated with measured data from a 0.35 μm CMOS process. Since the...
    Resource Type:
    Masters Thesis
    Full Text:
    considered. A single contact is 0.7 µm x 0.85 µm, two con- tacts are 0.7 µm x 1.5 µm, and four contacts are

  • Comparison and impact of substrate noise due to clocked and clockless circuitry

    Creator:
    Le, Jim K.
    Abstract:
    Delay insensitive asynchronous circuitry provides significant advantages with respect to substrate noise due to localized switching. The differences between the substrate noise from NULL Convention Logic (NCL) and traditional Clocked Boolean Logic (CBL) are described and analyzed based on measured results. A test chip fabricated in the TSMC 0.25 um...
    Resource Type:
    Masters Thesis
    Full Text:
    characteristic of NCL circuits as a result of localized switching. 25 0 0.2 0.4 0.6 0.8 1 x 10 −6 −0.3

  • A comparison of substrate noise coupling in heavily doped and lightly doped substrates for mixed-signal circuits

    Creator:
    Ayers, James S.
    Abstract:
    An analysis of substrate noise coupling in mixed-signal circuits has been performed in the TSMC 0.25 [mu]m lightly doped and heavily doped CMOS processes. Methods to minimize noise coupling in both the chip design and board design phases are presented along with techniques for accurate circuit simulation of noise coupling....
    Resource Type:
    Masters Thesis
    Full Text:
    contacts (injector and sensor) sized as 1000 m x 1000 im for case 1 and 300 m x 300 im for case 2 are

  • Contributions to substrate noise due to supply coupling and pin parasitics

    Creator:
    Adluri, Sirisha
    Abstract:
    This thesis presents the contributions to substrate noise due to supply coupling and the effect of pin parasitics on the substrate noise generated by digital circuits. Various sources of substrate noise and their effect on analog circuits sharing the same substrate are discussed. A simulation approach to isolate the various...
    Resource Type:
    Masters Thesis
    Full Text:
    and source are tied together ....................................... 59 x LIST OF TABLES Table ig

  • Silencer! : a tool for substrate noise coupling analysis

    Creator:
    Birrer, Patrick
    Abstract:
    This thesis presents Silencer!, a fully automated, schematic-driven tool for substrate noise coupling simulation and analysis. It has been integrated in the CADENCE DFII environment and seamlessly enables substrate coupling analysis in a standard mixed-signal design flow. Silencer! aids IC designers in the analysis of substrate noise coupling at different...
    Resource Type:
    Masters Thesis
    Full Text:
    various conditions (A - G) is shown in Table 4.1 .................... 54 x LIST OF FIGURES