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Filtering by: Creator Ortíz-Lozano, Leonardo D. Remove constraint Creator: Ortíz-Lozano, Leonardo D. Degree Field Electrical and Computer Engineering Remove constraint Degree Field: Electrical and Computer Engineering

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  • The dynamic simultaneous multithreaded processor

    Creator:
    Ortiz-Arroyo, Daniel
    Abstract:
    This dissertation investigates diverse techniques to support multithreading in modern high performance processors. The mechanisms studied expand the architecture of a high performance superscalar processor to control efficiently the interaction between software-controlled and hardware-controlled multithreading. Additionally, dynamic speculative mechanisms are proposed to exploit thread-level-parallelism (TLP) and instruction-level-parallelism (ILP) on a...
    Resource Type:
    Dissertation
    Full Text:
    AN ABSTRACT OF THE THESIS OF Daniel Ortiz-Arroyo for the degree

  • Improving motion estimation with evolvable search algorithms

    Creator:
    Dill, Martin D.
    Abstract:
    Until now the topic of motion estimation, as used in video compression, has been dominated by search methodologies which are modifications of an exhaustive search. This research takes a completely new approach by applying two evolvable search algorithms, the Genetic Algorithm and the Genetic Program, to the area of motion...
    Resource Type:
    Masters Thesis
    Full Text:
    AN ABSTRACT OF THE THESIS OF Martin D. Dill for the degree of Master of Science in Electrical and

  • Dependency speculation in dynamic simultaneous multi-threading

    Creator:
    Nelson, Jarrod A.
    Abstract:
    The purpose of this thesis is to explore dependency speculation in Dynamic Simultaneous Multi-Threading (DSMT). DSMT is a microprocessor architecture which attempts to extract Thread Level Parallelism (TLP) from single-threaded programs at run-time. This is accomplished by running multiple iterations of program loops in parallel. The DSMT architecture was originally...
    Resource Type:
    Masters Thesis
    Full Text:
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  • Low power high resolution data converter in digital CMOS technology

    Creator:
    Zheng, Zhiliang
    Abstract:
    The advance of digital IC technology has been very fast, as shown by rapid development of DSP, digital communication and digital VLSI. Within electronic signal processing, analog-to-digital conversion is a key function, which converts the analog signal into digital form for further processing. Recently, low-voltage and low-power have become also...
    Resource Type:
    Masters Thesis
    Full Text:
    design of low-power high- performance A/D converters in CMOS technology, and the non-ideal switched

  • The dynamic speculation and performance prediction of parallel loops

    Creator:
    Zier, David A.
    Abstract:
    General purpose computer systems have seen increased performance potential through the parallel processing capabilities of multicore processors. Yet this potential performance can only be attained through parallel applications, thus forcing software developers to rethink how everyday applications are designed. The most readily form of Thread Level Parallelism (TLP) within any...
    Resource Type:
    Dissertation
    Full Text:
    Multithreading (D-SpMT), which can extract multiple threads from a sequential program without compiler support

  • New hardware algorithms and designs for Montgomery modular inverse computation in Galois Fields GF(p) and GF(2 [superscript n])

    Creator:
    Gutub, Adnan Abdul-Aziz
    Abstract:
    The computation of the inverse of a number in finite fields, namely Galois Fields GF(p) or GF(2ⁿ), is one of the most complex arithmetic operations in cryptographic applications. In this work, we investigate the GF(p) inversion and present several phases in the design of efficient hardware implementations to compute the...
    Resource Type:
    Dissertation
    Full Text:
    and Computer Engineering Chair of the Department of Electrical and Compute Engineering D I

  • Hardware design of scalable and unified modular division and Montgomery multiplication

    Creator:
    Park, Song Jun
    Abstract:
    Modular arithmetic is a basic operation for many cryptography applications such as public key cryptography, key exchange algorithms, digital signatures, and elliptic curve cryptography. Therefore, fast and efficient hardware design of modular division and multiplication is proposed for implementation of cryptography system with intent to achieve information security. The hardware...
    Resource Type:
    Masters Thesis
    Full Text:
    4.2.2 Leonardo Synthesis Results . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.3 Result

  • ASIC design and implementation of a parallel exponentiation algorithm using optimized scalable Montgomery multipliers

    Creator:
    Kurniawan, Budiyoso
    Abstract:
    Modular exponentiation and modular multiplication are the most used operations in current cryptographic systems. Some well-known cryptographic algorithms, such as RSA, Diffie-Hellman key exchange, and DSA, require modular exponentiation operations. This is performed with a series of modular multiplications to the extent of its exponent in a certain fashion depending...
    Resource Type:
    Masters Thesis
    Full Text:
    ........................................................ 90 Appendix D. Kernel Design Tool Input and Output Example ................................ 100 iv

  • Radix-4 ASIC design of a scalable Montgomery modular multiplier using encoding techniques

    Creator:
    Tawalbeh, Lo'ai
    Abstract:
    Modular arithmetic operations (i.e., inversion, multiplication and exponentiation) are used in several cryptography applications, such as decipherment operation of RSA algorithm, Diffie-Hellman key exchange algorithm, elliptic curve cryptography, and the Digital Signature Standard including the Elliptic Curve Digital Signature Algorithm. The most important of these arithmetic operations is the modular...
    Resource Type:
    Masters Thesis
    Full Text:
    is mapped to the mux enable (when it is one the output will be zero). D is mapped to the mux select

  • Digital implementation of a mismatch-shaping successive-approximation ADC

    Creator:
    Coe, Matthew T.
    Abstract:
    Utilizing a two-capacitor topology, the digital implementation of an audio-band successive-approximation analog-to-digital converter (ADC) is explored in the context of mismatch-shaping where the mismatch estimates are accurate to the first order. A second-order Δ∑ loop was found to be effective in system simulations given a 0.1% capacitor mismatch. Spectral analysis...
    Resource Type:
    Masters Thesis
    Full Text:
    -independent multiplication scheme is pre- sented that should allow algorithmic A/D operation that is not