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Filtering by: Subject Integrated circuits -- Very large scale integration Remove constraint Subject: Integrated circuits -- Very large scale integration Degree Level Doctoral Remove constraint Degree Level: Doctoral

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  • The analysis and synthesis of a parallel sorting engine

    Creator:
    Ahn, Byoungchul
    Abstract:
    This thesis is concerned with the development of a unique parallel sort-merge system suitable for implementation in VLSI. Two new sorting subsystems, a high performance VLSI sorter and a four-way merger, were also realized during the development process. In addition, the analysis of several existing parallel sorting architectures and algorithms...
    Resource Type:
    Dissertation
    Full Text:
    Recent advances in very large scale integration (VLSI) technology have resulted in a significant rate of

  • Mapping of recursive algorithms onto multi-rate arrays

    Creator:
    Zheng, Yue-Peng
    Abstract:
    In this dissertation, multi-rate array (MRA) architecture and its synthesis are proposed and developed. Using multi-coordinate systems (MCS), a unified theory for mapping algorithms from their original algorithmic specifications onto multi-rate arrays is developed. A multi-rate array is a grid of processors in which each interconnection may have its own...
    Resource Type:
    Dissertation
    Full Text:
    performance computing can be achieved by using application specific computers that utilize Very-Large-Scale

  • Analysis and applications of layered multiconductor coupled slot and strip-slot structures

    Creator:
    Luo, Sifen
    Abstract:
    Layered multiconductor coupled slot and strip-slot structures are characterized by introducing the full-wave modal analysis as well as the quasi-TEM spectral domain technique. In the modal analysis, the electric and magnetic fields are constructed in terms of modal fields in different regions. Application of the boundary conditions at interfaces for...
    Resource Type:
    Dissertation
    Full Text:
    two decades, significant progress has been made in the area of very- large-scale-integrated (VLSI

  • Efficient decoder design for error correction codes

    Creator:
    He, Jinjin
    Abstract:
    Error correction codes (ECCs) have been widely used in communication systems and storage devices. Nowadays, the rapid development of integrated circuit technologies makes feasible the implementation of powerful ECCs such as turbo code and low-density parity-check (LDPC) code. However, these high-performance codes require complex decoding algorithms, resulting in large hardware...
    Resource Type:
    Dissertation
    Full Text:
    systems [1]. Historically, very-large-scale integration (VLSI) technique plays an important role for the

  • Low-complexity high-speed VLSI design of low-density parity-check decoders

    Creator:
    Cui, Zhiqiang
    Abstract:
    Low-Density Parity-check (LDPC) codes have attracted considerable attention due to their capacity approaching performance over AWGN channel and highly parallelizable decoding schemes. They have been considered in a variety of industry standards for the next generation communication systems. In general, LDPC codes achieve outstanding performance with large codeword lengths (e.g.,...
    Resource Type:
    Dissertation
    Full Text:
    complexity of typical decoding algorithm such as MLD becomes very large as codeword length or encoder

  • Efficient VLSI architectures for MIMO and cryptography systems

    Creator:
    Li, Qingwei
    Abstract:
    Multiple-input multiple-output (MIMO) communication systems have recently been considered as one of the most significant technology breakthroughs for modern wireless communications, due to the higher spectral efficiency and improved link reliability. The sphere decoding algorithm (SDA) has been widely used for maximum likelihood (ML) detection in MIMO systems. It is...
    Resource Type:
    Dissertation
    Full Text:
    the emerging standards such as IEEE 802.16. Therefore, the research in the MIMO systems is very