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Filtering by: Subject Switched capacitor circuits -- Design and construction Remove constraint Subject: Switched capacitor circuits -- Design and construction Degree Name Master of Science (M.S.) Remove constraint Degree Name: Master of Science (M.S.)

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  • Low-voltage switched-capacitor circuits

    Creator:
    Bidari, Emad
    Abstract:
    In recent years, the rapidly growth of CMOS technology has evolved towards submicron and deep-submicron features. Due to smaller device sizes, and significant demand for low-power designs, the maximum allowable power supply voltage is restricted. So far, two solutions; clock boosting and switched opamp schemes have been proposed. The material...
    Resource Type:
    Masters Thesis
    Full Text:
    and constructive critiques that put me a step ahead in understanding analog circuit design. I thank

  • Fast opamp-free delta sigma modulator

    Creator:
    Thomas, Daniel E.
    Abstract:
    Switched-capacitor (SC) circuits are commonly used for analog signal processing because they can be used to realize precision filters and data converters on an integrated circuit (IC). However, for high speed applications SC circuit operating speeds are limited by the internally-compensated opamps found in SC integrators, a common building block...
    Resource Type:
    Masters Thesis
    Full Text:
    ) circuits are commonly used in integrated circuit (IC) design due to their efficient use of die space, and

  • Design of high efficiency step-down switched capacitor DC/DC converter

    Creator:
    Ma, Mengzhe
    Abstract:
    Recently, switched capacitor DC/DC converters are extensively used in portable electronic devices because they feature many advantages, such as high efficiency, small package, low quiescent current, minimal external components and low cost. In this thesis, two step-down switched capacitor DC/DC converters are designed. One has the fixed output options 1.5V,...
    Resource Type:
    Masters Thesis
    Full Text:
    4.5 Design of the Switched Capacitor Array ........................................... 25 4.6 Circuit

  • Low voltage techniques for pipelined analog-to-digital converters

    Creator:
    Carnes, Joshua Kenneth
    Abstract:
    To realize pipelined ADCs in deep-submicron processes, low voltage techniques must be developed to work around problems created by limited supply voltages such as the floating switch dead zone, reduced SNR, and reduced OpAmp performance. This thesis analyzes standard and low voltage design issues for pipelined ADCs and proposes a...
    Resource Type:
    Masters Thesis
    Full Text:
    . Chapter 3 covers circuit-level design considerations including tradeoffs and sources of error. Chapter 4

  • Low noise FSCL digital circuits for decimation filter

    Creator:
    Wong, Man Wa
    Abstract:
    A new circuit technique called Folded Source Coupled Logic (FSCL) has been developed to implement the digital section of mixed-signal IC applications. This FSCL circuit technique offers the advantage of low overlap current spikes during the switching transitions of conventional CMOS gates. This overlap current spike has become one of...
    Resource Type:
    Masters Thesis
    Full Text:
    filter 42 LIST OF TABLES Table Page 1 Comparison of a 4-bit CLA and 4-bit CSA 16 2 Design

  • Reaction kinetics and mass transport in the electroless deposition of copper

    Creator:
    Ninosky, Joseph M.
    Resource Type:
    Masters Thesis
    Full Text:
    and Mass Transport in the Electroless Deposition of Copper. Milo Koretsky Electroless copper

  • Low power scheduling schemes that consider latency and resource constraints at multiple voltages

    Creator:
    Huang, Shyh-Sen
    Abstract:
    Power reduction can be achieved at many different levels, such as architecture, algorithm, logic, and transistor levels in circuit design. This thesis focuses on low power scheduling at the algorithm level. We present a latency-constrained scheduling and a latency and resource constrained scheduling, which minimize power consumption for the resources...
    Resource Type:
    Masters Thesis
    Full Text:
    (algorithm), logic, circuit, and layout level. The process to design a low-power system has been

  • Switched-current logic for digital circuit design

    Creator:
    Subramanian, Vivek
    Resource Type:
    Masters Thesis
    Full Text:
    Switched-current logic for digital circuit design AN

  • Comparison and impact of substrate noise due to clocked and clockless circuitry

    Creator:
    Le, Jim K.
    Abstract:
    Delay insensitive asynchronous circuitry provides significant advantages with respect to substrate noise due to localized switching. The differences between the substrate noise from NULL Convention Logic (NCL) and traditional Clocked Boolean Logic (CBL) are described and analyzed based on measured results. A test chip fabricated in the TSMC 0.25 um...
    Resource Type:
    Masters Thesis
    Full Text:
    switched on and off rapidly as the digital gate changes state. In a typical CBL design, a large number of

  • Model and design of cmos phase-locked loop

    Creator:
    Shum, Daniel K.
    Abstract:
    This thesis will examine the model and design technique of a self-contained analog CMOS Phase-Locked Loop. This system has an adaptable filter and demodulator for an oscillating frequency of up to 1000 KHz and it is programmable by means of an external resistor and capacitor. The first topic to be...
    Resource Type:
    Masters Thesis
    Full Text:
    LOW-PASS FILTER 10 3.4 LOCK AND CAPTURE RANGES 13 CHAPTER 4 CIRCUIT DESCRIPTION AND DESIGN