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Filtering by: Funding statement This work was supported by the Semiconductor Research Corporation (SRC), and the Center for Design Analog-Digital Integrated Circuits (CDADIC). Remove constraint Funding statement: This work was supported by the Semiconductor Research Corporation (SRC), and the Center for Design Analog-Digital Integrated Circuits (CDADIC). Degree Name Master of Science (M.S.) Remove constraint Degree Name: Master of Science (M.S.)

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  • Analysis and modeling of microstrip on-chip interconnects on silicon substrate

    Creator:
    Lan, Hai
    Abstract:
    The electrical performance of on-chip interconnects has become a limiting factor to the performance of modern integrated circuits including RFICs, mixed-signal circuits, as well as high-speed VLSI circuits due to increasing operating frequencies, chip areas, and integration densities. It is advantageous to have fast and accurate closed-form expressions for the...
    Resource Type:
    Masters Thesis
    Full Text:
    interconnects to facilitate fast simulation and computer-aided design (CAD) of integrated circuits. This the

  • Analysis and modeling of coplanar on-chip interconnects on silicon substrates

    Creator:
    Luoh, Yi
    Abstract:
    The electrical behavior of on-chip interconnects has become a dominant factor in silicon-based high speed, RF, and mixed-signal integrated circuits. In particular, the frequency-dependent loss mechanisms in heavily-doped silicon substrates can have a large influence on the transmission characteristics of on-chip interconnects. To optimize the performance of the integrated circuit,...
    Resource Type:
    Masters Thesis
    Full Text:
    this project, funded by the Center of Design of Analog- Digital Integrated Circuits (CDADIC). TABLE

  • Substrate coupling macromodel for lightly doped CMOS processes

    Creator:
    Koteeswaran, Mohanalakshmi
    Abstract:
    A scalable macromodel for substrate noise coupling in lightly doped substrates with and without a buried layer has been developed. This model is based on Z-parameters and is scalable with contact size and separation. This model requires process dependent parameters that can be extracted easily from a small number of...
    Resource Type:
    Masters Thesis
    Full Text:
    Semiconductor Research Corporation(SRC) for supporting this and related work and Teradyne for helping with the

  • Electrical recommendations and formulas for metal fill in radio-frequency integrated circuits

    Creator:
    Gaskill, Steven
    Abstract:
    With increasing transistor operating frequencies, interconnects and passive devices are becoming performance limiters in integrated circuit (IC) designs. To combat this, the interconnect layers above the active silicon are trending toward low-κ dielectrics and Cu metallization. The use of these new materials has popularized chemical mechanical polishing (CMP) to planarize...
    Resource Type:
    Masters Thesis
    Full Text:
    has been supported by CDADIC and I would like to thank the member companies for the many helpful

  • Metal fill considerations for on-chip interconnects and spiral inductors

    Creator:
    Shilimkar, Vikas S.
    Abstract:
    Variability in circuit performance due to process defects is a major concern in integrated circuit (IC) fabrication. Advanced IC manufacturing processes employ Chemical-Mechanical Polishing (CMP) for planarization of oxide and metal layers. CMP defects result in variations in the oxide and metal topographical profile. To reduce these topographical variations, electrically...
    Resource Type:
    Masters Thesis
    Full Text:
    been a great help for all administrative matters. This project is supported by CDADIC/SRC and I would

  • Algorithms and simulators for coupled device/circuit simulation

    Creator:
    Dudar, Taras
    Abstract:
    Algorithms and simulators comprised of SPICE3 as a circuit level simulator and two device simulators EOFLOW and PROPHET for accurate simulation of new types of devices are presented in this thesis. An integration of EOFLOW with SPICE3 creates a capability for efficient simulation of a system containing interconnected electroosmotic flow...
    Resource Type:
    Masters Thesis
    Full Text:
    ]. 7 In the late l980s. research work was focused on a mixed-level device and circuit simulator

  • Low frequency noise and the upconverted phase noise effects in NMOSFET circuits

    Creator:
    Xie, Dingming
    Resource Type:
    Masters Thesis
    Full Text:
    . Thanks to the National Science Foundation Center for the Design of AnaloglDigital Integrated Circuits

  • A comparison of substrate noise coupling in lightly and heavily doped CMOS processes for 2.4 GHz LNA's

    Creator:
    Hazenboom, Duncan S.
    Abstract:
    Three types of low noise amplifiers operating at 2.4GHz were designed. They are the commonly used single-ended and differential amplifiers as well as a new quasi-differential amplifier. The substrate noise injected into these amplifiers is examined for both heavily and lightly doped CMOS substrates. For the single-ended amplifier the noise...
    Resource Type:
    Masters Thesis
    Full Text:
    method to improve some of the measurements. This work has been supported financially in part by SRC

  • Characteristics of RC digital filters as bandpass circuits

    Creator:
    Hancock, Robert James
    Abstract:
    One of the most promising methods of constructing bandpass filters without inductors is the RC digital filter. It is simply a number of parallel RC branches which are sequentially switched between the source and the load. If the source signal is at the same frequency as the switching rate of...
    Resource Type:
    Masters Thesis
    Full Text:
    promise for digital filters lies in the area of integrated circuits, since inductors cannot be made by

  • Algorithms and tools for optimization of integrated RF VCOs

    Creator:
    Kratyuk, Volodymyr
    Abstract:
    This thesis presents algorithms and tools for the automated design of RF LC CMOS voltage controlled oscillators (VCOs) with low phase noise given a set of specifications. The electromagnetic solver, ASITIC, combined with the circuit simulator, SpectreRF, allows optimization of the VCO circuit parameters and inductor layout. This approach gives...
    Resource Type:
    Masters Thesis
    Full Text:
    research has been supported and funded by CDADIC, NSF and SRC. I thank them all for the opportunity they