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Filtering by: Has journal Journal of Extension File Format application/pdf Resource Type Masters Thesis Subject Substrate noise

An efficient modeling approach for substrate noise coupling analysis with multiple contacts in heavily doped CMOS processes

Creator:

Özis, Hatice Dicle

Abstract:

A computationally efficient and accurate substrate noise coupling model for multiple contacts in heavily doped CMOS processes is presented and validated with simulations and experimental data. The model is based on Z parameters that are scalable with contact separation and size. This results in fast extraction of substrate resistances for...

Resource Type:

Masters Thesis

Full Text:

....................................................... 1 2 MACROMODEL ......................................................... 3 3 EXTENSION OF
Ground tap placement and sizing to minimize substrate noise coupling in RF LNAs

Creator:

Sundaresan, Arathi

Abstract:

The substrate noise injected by a stepped buffer circuit into two single-ended 1.5GHz low noise amplifiers is examined for a heavily doped 0.25µm CMOS process. The difference in the LNA noise rejection is characterized as a function of the size and placement of substrate contacts. The use of a resistive...

Resource Type:

Masters Thesis

Full Text:

1 AN ABSTRACT OF THE THESIS OF Arathi Sundaresan
A substrate noise coupling model for lightly doped CMOS processes

Creator:

Sadate, Aline C.

Abstract:

This thesis presents a design-oriented model for lightly doped CMOS substrates. The model predicts the substrate noise coupling between noisy digital and sensitive analog blocks in the early stages of the design. The model scales with the size and separation of these blocks and it is validated with device simulations...

Resource Type:

Masters Thesis

Full Text:

: simulations and power distribution synthesis," IEEE Journal of Solid-State Circuits, vol. 29, pp. 226- 238

ScholarsArchive@OSU

An efficient modeling approach for substrate noise coupling analysis with multiple contacts in heavily doped CMOS processes

Ground tap placement and sizing to minimize substrate noise coupling in RF LNAs

A substrate noise coupling model for lightly doped CMOS processes

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