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Filtering by: Committee Member Kimura, Shoichi File Format application/pdf Subject Cache memory

Single-level dynamic register caching architecture for high-performance superscalar processors

Creator:

Liebert, John A.

Abstract:

The amount of instruction level parallelism (ILP) that can be exploited depends greatly on the size of the instruction window and the number of in-flight instructions the processor can support. However, this requires a register file with a large set of physical registers for renaming and multiple ports to provide...

Resource Type:

Masters Thesis

Full Text:

, Dr. Thinh Nguyen, and Dr. Shoichi Kimura for serving on my defense committee and for their helpful