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  • Low-complexity high-speed VLSI design of low-density parity-check decoders

    Creator:
    Cui, Zhiqiang
    Abstract:
    Low-Density Parity-check (LDPC) codes have attracted considerable attention due to their capacity approaching performance over AWGN channel and highly parallelizable decoding schemes. They have been considered in a variety of industry standards for the next generation communication systems. In general, LDPC codes achieve outstanding performance with large codeword lengths (e.g.,...
    Resource Type:
    Dissertation
    Full Text:
    considers various VLSI design issues of LDPC decoder and develops efficient approaches for reducing memory

  • Efficient VLSI architectures for MIMO and cryptography systems

    Creator:
    Li, Qingwei
    Abstract:
    Multiple-input multiple-output (MIMO) communication systems have recently been considered as one of the most significant technology breakthroughs for modern wireless communications, due to the higher spectral efficiency and improved link reliability. The sphere decoding algorithm (SDA) has been widely used for maximum likelihood (ML) detection in MIMO systems. It is...
    Resource Type:
    Dissertation
    Full Text:
    design for the MIMO systems. It includes the algorithms simplification, and transformations, hardware