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  • Power reduction of MPEG video decoding for mobile multimedia systems

    Creator:
    Lewis, James M.
    Abstract:
    The purpose of this thesis is to explore methods which can reduce the power dissipation of a mobile system while decoding MPEG video. MPEG decoding is a microprocessor intensive process that makes heavy use of both the L1 and L2 caches as well as main memory. The heavy load placed...
    Resource Type:
    Masters Thesis
    Full Text:
    : ______________________________________________________ Ben Lee The purpose of this thesis is to explore methods which can reduce the power

  • Instruction fetching, scheduling, and forwarding in a dynamic multithreaded processor

    Creator:
    Browning, Adam W.
    Abstract:
    Dynamic multithreaded processors attempt to increase the performance of a single sequential program by dynamically extracting threads from sources such as loop iterations. The scheduling of instructions in such a processor plays a vital role in the amount of thread level parallelism that can be extracted and thus the overall...
    Resource Type:
    Masters Thesis
    Full Text:
    : ______________________________________________________ Ben Lee Dynamic multithreaded processors attempt to increase the performance of a single

  • Single-level dynamic register caching architecture for high-performance superscalar processors

    Creator:
    Liebert, John A.
    Abstract:
    The amount of instruction level parallelism (ILP) that can be exploited depends greatly on the size of the instruction window and the number of in-flight instructions the processor can support. However, this requires a register file with a large set of physical registers for renaming and multiple ports to provide...
    Resource Type:
    Masters Thesis
    Full Text:
    : ______________________________________________________ Ben Lee The amount of instruction level parallelism (ILP) that can be exploited

  • Asymmetric clustering using a register cache

    Creator:
    Morrison, Roger Allen
    Abstract:
    Conventional register files spread porting resources uniformly across all registers. This paper proposes a method called Asymmetric Clustering using a Register Cache (ACRC). ACRC utilizes a fast register cache that concentrates valuable register file ports to the most active registers thereby reducing the total register file area and power consumption....
    Resource Type:
    Masters Thesis
    Full Text:
    . Abstract approved: Ben Lee Conventional register files spread porting resources

  • Dependency speculation in dynamic simultaneous multi-threading

    Creator:
    Nelson, Jarrod A.
    Abstract:
    The purpose of this thesis is to explore dependency speculation in Dynamic Simultaneous Multi-Threading (DSMT). DSMT is a microprocessor architecture which attempts to extract Thread Level Parallelism (TLP) from single-threaded programs at run-time. This is accomplished by running multiple iterations of program loops in parallel. The DSMT architecture was originally...
    Resource Type:
    Masters Thesis