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Filtering by: Creator Li, Cheng Remove constraint Creator: Li, Cheng Non-Academic Affiliation Oregon State University. Graduate School Remove constraint Non-Academic Affiliation: Oregon State University. Graduate School Subject Metal oxide semiconductors, Complementary Remove constraint Subject: Metal oxide semiconductors, Complementary

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  • Analysis and design on low-power short-range radios for wireless body area networks

    Creator:
    Cheng, Jiao
    Abstract:
    The release of the IEEE802.15.6 standard has led to increased interest in low-power technologies for wireless body-area-networks (WBANs). The power dissipation, supply voltage, and die area are some of the most important criteria for successful WBAN implementations. Digital-intensive RX architectures can potentially result in sub-1V operation with significant reductions in...
    Resource Type:
    Dissertation
    Full Text:
    Cheng, Jinzhou Cao, Tao Wang, Wei Li, Xin Meng, Youngho Jung, Jiamin Lin, Chao Shi, Ronghua Ni, Yue Hu

  • Design of 28 GHz Low-Power Phased-Array Receiver Frontend in CMOS

    Creator:
    Garg, Robin
    Abstract:
    This work presents the design and implementation of a low power phased-array receiver frontend at 28 GHz in 65 nm CMOS. The frontend incorporates a low- power low-noise amplifier(LNA) and a passive reflection-type phase shifter (RTPS) capable of providing 360° phase shift with 5-bit phase resolution and low loss variation....
    Resource Type:
    Masters Thesis

  • An efficient modeling approach for substrate noise coupling analysis with multiple contacts in heavily doped CMOS processes

    Creator:
    Özis, Hatice Dicle
    Abstract:
    A computationally efficient and accurate substrate noise coupling model for multiple contacts in heavily doped CMOS processes is presented and validated with simulations and experimental data. The model is based on Z parameters that are scalable with contact separation and size. This results in fast extraction of substrate resistances for...
    Resource Type:
    Masters Thesis
    Full Text:
    Fetche, John NlcNitt for their help in my first semester at WSU, Cheng-gang Xu for his software EPIC

  • Design of low power 2.4GHz CMOS LC balanced oscillators with low phase noise and large tuning range

    Creator:
    Seshan, Nilakantan
    Abstract:
    The design of two 2.4GHz CMOS LC balanced oscillators in the 0.25μm National BiCMOS process for Bluetooth specifications is presented. These oscillators achieve low phase noise with low power consumption. At a frequency offset of 500KHz from the 2.11GHz carrier, the measured phase noise is -101.9dBc/Hz for the NMOS oscillator...
    Resource Type:
    Masters Thesis
    Full Text:
    , Zhimin, Oleg, Yuxian, Jose' and Cheng-gang for helping me with technical problems. I especially thank my

  • Comparison and analysis of jitter in CMOS ring oscillators

    Creator:
    Natesan, Peroly
    Abstract:
    A comparison and analysis of jitter for five different architectures of ring oscillators using a novel simulation technique developed by Professor Forbes' group is presented. Ring oscillators have become an essential building block in many digital and synchronous communications system due to their integrated nature and are widely used in...
    Resource Type:
    Masters Thesis

  • Design techniques for time based data converters

    Creator:
    Gande, Manideep
    Abstract:
    Modern day CMOS processes are characterized by voltage scaling and geometry scaling. Geometry scaling helps reduce gate delays, thereby aiding in the design of data converters which use time based processing. Another artifact of geometry scaling is the increase in complexity of digital circuitry available on traditional analog ICs, as...
    Resource Type:
    Dissertation
    Full Text:
    , Praveen Prabha, Rajesh Inti, Sameer, Tesjasvi Anand, Tao Wang, Brian Young, Wei Li, Sai Praneeth are

  • Energy efficient communication across on-chip wires in digital CMOS

    Creator:
    Postman, Jacob
    Abstract:
    For the past half century, CMOS process scaling has followed Moore's law, approximately doubling transistor density every 18 months. While locally routed wires have generally scaled with transistor size, longer wires have scaled at a slower rate and in some cases have grown larger as chip size and complexity have...
    Resource Type:
    Dissertation
    Full Text:
    heads off to his next adventure. I can not thank Tushar Krishna and Professor Li-Shiuan Peh enough for