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Filtering by: Creator Anand, Satish Kumar Remove constraint Creator: Anand, Satish Kumar Non-Academic Affiliation Oregon State University. Graduate School Remove constraint Non-Academic Affiliation: Oregon State University. Graduate School

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  • Majority logic circuits

    Creator:
    Anand, Satish Kumar
    Abstract:
    This thesis considers the worst-case design of transistor circuits for the realization of Majority Logic. First the meaning of Majority Logic is discussed. The requirement of an odd number of inputs for the realization of Majority Logic is justified. The usefulness of Majority Logic in synthesizing a Boolean expression is...
    Resource Type:
    Masters Thesis
    Full Text:
    SATISH KUMAR ANAND for the M. S. in Electrical Engineering (Name) (Degree) (Major) Date thesis is