Search Constraints

Start Over
Filtering by: Subject Equalizers (Electronics) -- Design and construction Remove constraint Subject: Equalizers (Electronics) -- Design and construction Non-Academic Affiliation Oregon State University. Graduate School Remove constraint Non-Academic Affiliation: Oregon State University. Graduate School

Search Results

  • Equalizer design for MDFE channels using nonlinear optimization

    Creator:
    Onu, Dan
    Abstract:
    Decision feedback equalization (DFE) is a sampled-data technique used for data recovery in digital communications channels. Multi-level decision feedback equalization (MDFE) has been developed for channels using the 2/3(1,7) RLL code. The optimum detector for a digital communication channel affected by ISI and noise consists of a matched filter, followed...
    Resource Type:
    Masters Thesis
    Full Text:
    the APF, and the type and corner frequency of the LPF. A symbolic approach to the equalizer design

  • Design of high-speed low-power analog CMOS decision feedback equalizers

    Creator:
    Su, Wenjun
    Abstract:
    Decision feedback equalizer (DFE) is an effective method to remove inter-symbol interference (ISI) from a disk-drive read channel. Analog IC implementations of DFE potentially offers higher speed, smaller die area, and lower power consumption when compared to their digital counterparts. Most of the available DFE equalizers were realized by using...
    Resource Type:
    Masters Thesis
    Full Text:
    of Science in Electrical and Computer Engineerin presented on July 8th. 1996. Title: Design Of High

  • Design of high-speed adaptive parallel multi-level decision feedback equalizer

    Creator:
    Xiang, Yihai
    Abstract:
    Multi-level decision feedback equalization (MDFE) is an effective technique to remove inter-symbol interference (ISI) from disk readback signals, which uses the simple architecture of decision feedback equalization. Parallelism which doubles the symbol rate can be realized by setting the first tap of the feedback filter to zero. A mixed-signal implementation...
    Resource Type:
    Masters Thesis
    Full Text:
    Electrical and Computer Engineering presented on Feb. 26th, 1997. Title: Design of High-Speed Adaptive

  • A fast carry binary adder

    Creator:
    Bernhardt, Donn Eugene
    Abstract:
    This thesis describes the adder to be used with the Galaxy computer, which is to be constructed at Oregon State University. The need for faster, more reliable adders is discussed along with previous adder designs related to the Galaxy Fast Carry Adder. Both the logical design and circuit design of...
    Resource Type:
    Masters Thesis
    Full Text:
    the logical design and circuit design of the Galaxy Fast Carry Adder are discussed. Operating speed

  • A feasibility study on the use of arithmetic-memory registers in the design of digital computer systems

    Creator:
    Frank, Rudolph Joseph
    Abstract:
    The concept of combining arithmetic and memory capability on a single semiconductor chip has become practical from a system's viewpoint through the decreased cost of semiconductor memories and high circuit densities achieved through large scale integration. This paper describes a model for studying the feasibility of such systems. An arithmetic-memory...
    Resource Type:
    Dissertation
    Full Text:
    described. The state model proved to be a useful technique in the design of the system. Cost estimates and

  • The logical design of the NEBULA computer

    Creator:
    Boles, John Amos
    Abstract:
    Research in digital computers takes two paths: one uses the computer as a tool to reach certain objectives; on the other, the computer itself is the object of research. The NEBULA computer was built with the latter in mind. The system design and logical design are described here in detail....
    Resource Type:
    Dissertation

  • Design techniques for clocking high performance signaling systems

    Creator:
    Hanumolu, Pavan Kumar
    Abstract:
    Scaling of CMOS technology has progressed relentlessly for the past several decades. In order for this unprecedented scaling to benefit the performance of large digital systems, the communication bandwidth between integrated circuits (ICs) must scale accordingly. However, interconnect technology does not scale as aggressively, making communication between chips the major...
    Resource Type:
    Dissertation
    Full Text:
    being 3000 miles away and generously shared his vast knowledge on links design. Gu masterfully

  • Wideband discrete-time delta-sigma analog-to-digital converters with shifted loop delays

    Creator:
    Meng, Xin
    Abstract:
    Low-distortion architecture is widely used in wideband discrete-time switched-capacitor delta-sigma ADC design. However, it suffers from the power-hungry active adder and critical timing for quantization and dynamic element matching (DEM). To solve this problem, this dissertation presents a delta-sigma modulator architecture with shifted loop delays. In this project, shifted loop...
    Resource Type:
    Dissertation
    Full Text:
    Corporation (SRC), the Center for Design of Analog and Digital Integrated Circuits (CDIDIC), Texas

  • Ring amplification for switched capacitor circuits

    Creator:
    Hershberg, Benjamin Poris
    Abstract:
    A comprehensive and scalable solution for high-performance switched capacitor amplification is presented. Central to this discussion is the concept of ring amplification. A ring amplifier is a small modular amplifier derived from a ring oscillator that naturally embodies all the essential elements of scalability. It can amplify with accurate rail-to-rail...
    Resource Type:
    Dissertation
    Full Text:
    presented which explore the practical implementation options and design considerations relevant to ring

  • A study of basic building blocks of analog-to-digital delta-sigma modulators

    Creator:
    Guo, Yuhua
    Abstract:
    In this thesis, a novel Direct-Charge-Transfer (DCT) integrator structure is proposed, which can settle much faster than regular switch-capacitor integrators. A new Spread-Spectrum Dynamic Element Matching (SS-DEM) algorithm is also introduced, which can effectively spread or shape the nonlinearity error of multi-bit DAC in the feedback path, thus improve the...
    Resource Type:
    Masters Thesis
    Full Text:
    beginning of my research in school to the end of my study. And very happy to design a chip together. What