Search Constraints

Start Over
Filtering by: Subject Integrated circuits -- Very large scale integration Remove constraint Subject: Integrated circuits -- Very large scale integration Peer Reviewed No Remove constraint Peer Reviewed: No

Search Results

  • VLSI design methodologies and computer tools

    Creator:
    Lim, Daniel
    Abstract:
    The rapid development of semiconductor technology and the increasing complexity of VLSI chips have prompted both the industry and the academic community alike to take an indepth look at the VLSI design problem. Many design methodologies have been proposed and associated computer-aided tools developed. This thesis is a study of...
    Resource Type:
    Masters Thesis
    Full Text:
    count. Since the time of its inception, integrated circuit complexity has grown at an exponential rate

  • Acceleration of a heuristic PLA product term reduction program through complementation of the PLA specification

    Creator:
    Gilbert, John D.
    Abstract:
    Minimizing the number of product terms in a PLA implementation is a large step towards saving area on a VLSI chip using PLA logic. Due to the large amounts of computer time necessary to achieve this minimization, a number of heuristic approaches have been developed to provide near-optimal solutions in...
    Resource Type:
    Masters Thesis
    Full Text:
    integrated circuit taking as input m vari- ables and their complements, and having as output q functions

  • The architecture and design of a parallel sorting engine

    Creator:
    Bate, John G.
    Abstract:
    Sorting is typically a compute intensive operation used in many areas of industry. With improved technology, both in the VLSI and CAE areas, we can afford to develop hardware based database computers to move the work load off the main computer. In this thesis the architecture of a VLSI parallel...
    Resource Type:
    Masters Thesis
    Full Text:
    large scale integration. Each block of the architecture § See Section 2.2 on The Order Notation. 2

  • The analysis and synthesis of a parallel sorting engine

    Creator:
    Ahn, Byoungchul
    Abstract:
    This thesis is concerned with the development of a unique parallel sort-merge system suitable for implementation in VLSI. Two new sorting subsystems, a high performance VLSI sorter and a four-way merger, were also realized during the development process. In addition, the analysis of several existing parallel sorting architectures and algorithms...
    Resource Type:
    Dissertation
    Full Text:
    Recent advances in very large scale integration (VLSI) technology have resulted in a significant rate of

  • Mapping of recursive algorithms onto multi-rate arrays

    Creator:
    Zheng, Yue-Peng
    Abstract:
    In this dissertation, multi-rate array (MRA) architecture and its synthesis are proposed and developed. Using multi-coordinate systems (MCS), a unified theory for mapping algorithms from their original algorithmic specifications onto multi-rate arrays is developed. A multi-rate array is a grid of processors in which each interconnection may have its own...
    Resource Type:
    Dissertation
    Full Text:
    performance computing can be achieved by using application specific computers that utilize Very-Large-Scale

  • Time domain electromagnetic simulation of VLSI interconnects

    Creator:
    Falconer, Maynard C.
    Abstract:
    Current trends in integrated circuit technology are continuing towards physically smaller components and related structures. Interconnects between circuit components have reached sub-micron dimensions which can not be modeled accurately by the current ideal microstrip analysis based techniques. These techniques often assume that the structure being modeled is perfectly conducting, smooth,...
    Resource Type:
    Masters Thesis
    Full Text:
    VLSI INTERCONNECTS INTRODUCTION Current trends in integrated circuit technology are continuing

  • Application and analysis of CMOS FSCL for mixed-mode analog/digital ICs

    Creator:
    Chow, Andrew Siv-Anne
    Abstract:
    The new CMOS folded source-coupled logic (FSCL) technique intended for mixed-mode integrated circuits has been designed. It has advantages over conventional CMOS circuit in terms of reduced current spike, circuit delay, logic flexibility, and layout density. A simple CPU implemented in 2 μm CMOS technology with a 5.0 volt supply...
    Resource Type:
    Masters Thesis
    Full Text:
    . The mixed-mode analog/digital integrated circuit has not only provided high integration, but also

  • Design of complex digital blocks using folded source-coupled logic for mixed-mode applications

    Creator:
    Maskai, Sailesh R.
    Abstract:
    A series of complex digital blocks have been designed and fabricated using the newly developed current-mode differential CMOS logic family viz. the Folded Source-Coupled Logic ( FSCL ). The main feature of this logic family is the low current spikes generated during the switching transitions ( at least 2 orders...
    Resource Type:
    Masters Thesis
    Full Text:
    from National Science Foundation Center for the Design of Analog-Digital Integrated Circuits (CDADIC

  • Analysis and applications of layered multiconductor coupled slot and strip-slot structures

    Creator:
    Luo, Sifen
    Abstract:
    Layered multiconductor coupled slot and strip-slot structures are characterized by introducing the full-wave modal analysis as well as the quasi-TEM spectral domain technique. In the modal analysis, the electric and magnetic fields are constructed in terms of modal fields in different regions. Application of the boundary conditions at interfaces for...
    Resource Type:
    Dissertation
    Full Text:
    two decades, significant progress has been made in the area of very- large-scale-integrated (VLSI

  • Fully efficient pipelined VLSI arrays for solving toeplitz matrices

    Creator:
    Lee, Louis Wai-Fung
    Abstract:
    Fully efficient systolic arrays for the solution of Toeplitz matrices using Schur algorithm [1] have been obtained. By applying clustering mapping method [2], the complexity of the algorithm is 0(n) and it requires n/2 processing elements as opposed to n processing elements developed elsewhere [1]. The motivation of this thesis...
    Resource Type:
    Masters Thesis
    Full Text:
    decreased by factor of 2. The efficiency is n+1 E 2n-1 For very large number of n, E will be close to 1