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  • VLSI design methodologies and computer tools

    Creator:
    Lim, Daniel
    Abstract:
    The rapid development of semiconductor technology and the increasing complexity of VLSI chips have prompted both the industry and the academic community alike to take an indepth look at the VLSI design problem. Many design methodologies have been proposed and associated computer-aided tools developed. This thesis is a study of...
    Resource Type:
    Masters Thesis
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    count. Since the time of its inception, integrated circuit complexity has grown at an exponential rate

  • Acceleration of a heuristic PLA product term reduction program through complementation of the PLA specification

    Creator:
    Gilbert, John D.
    Abstract:
    Minimizing the number of product terms in a PLA implementation is a large step towards saving area on a VLSI chip using PLA logic. Due to the large amounts of computer time necessary to achieve this minimization, a number of heuristic approaches have been developed to provide near-optimal solutions in...
    Resource Type:
    Masters Thesis
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    integrated circuit taking as input m vari- ables and their complements, and having as output q functions

  • The architecture and design of a parallel sorting engine

    Creator:
    Bate, John G.
    Abstract:
    Sorting is typically a compute intensive operation used in many areas of industry. With improved technology, both in the VLSI and CAE areas, we can afford to develop hardware based database computers to move the work load off the main computer. In this thesis the architecture of a VLSI parallel...
    Resource Type:
    Masters Thesis
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    large scale integration. Each block of the architecture § See Section 2.2 on The Order Notation. 2

  • Time domain electromagnetic simulation of VLSI interconnects

    Creator:
    Falconer, Maynard C.
    Abstract:
    Current trends in integrated circuit technology are continuing towards physically smaller components and related structures. Interconnects between circuit components have reached sub-micron dimensions which can not be modeled accurately by the current ideal microstrip analysis based techniques. These techniques often assume that the structure being modeled is perfectly conducting, smooth,...
    Resource Type:
    Masters Thesis
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    VLSI INTERCONNECTS INTRODUCTION Current trends in integrated circuit technology are continuing

  • Application and analysis of CMOS FSCL for mixed-mode analog/digital ICs

    Creator:
    Chow, Andrew Siv-Anne
    Abstract:
    The new CMOS folded source-coupled logic (FSCL) technique intended for mixed-mode integrated circuits has been designed. It has advantages over conventional CMOS circuit in terms of reduced current spike, circuit delay, logic flexibility, and layout density. A simple CPU implemented in 2 μm CMOS technology with a 5.0 volt supply...
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    Masters Thesis
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    . The mixed-mode analog/digital integrated circuit has not only provided high integration, but also

  • Design of complex digital blocks using folded source-coupled logic for mixed-mode applications

    Creator:
    Maskai, Sailesh R.
    Abstract:
    A series of complex digital blocks have been designed and fabricated using the newly developed current-mode differential CMOS logic family viz. the Folded Source-Coupled Logic ( FSCL ). The main feature of this logic family is the low current spikes generated during the switching transitions ( at least 2 orders...
    Resource Type:
    Masters Thesis
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    from National Science Foundation Center for the Design of Analog-Digital Integrated Circuits (CDADIC

  • Fully efficient pipelined VLSI arrays for solving toeplitz matrices

    Creator:
    Lee, Louis Wai-Fung
    Abstract:
    Fully efficient systolic arrays for the solution of Toeplitz matrices using Schur algorithm [1] have been obtained. By applying clustering mapping method [2], the complexity of the algorithm is 0(n) and it requires n/2 processing elements as opposed to n processing elements developed elsewhere [1]. The motivation of this thesis...
    Resource Type:
    Masters Thesis
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    decreased by factor of 2. The efficiency is n+1 E 2n-1 For very large number of n, E will be close to 1

  • A micro data flow (MDF) : a data flow approach to self-timed VLSI system design for DSP

    Creator:
    Merani, Lalit T.
    Abstract:
    Synchronization is one of the important issues in digital system design. While other approaches have been intriguing, up until now a globally clocked timing discipline has been the dominant design philosophy. However, we have reached the point, with advances in technology, where other options should be given serious consideration. VLSI...
    Resource Type:
    Masters Thesis
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    in short lengths and is very suitable for layout in an integrated circuit. Also note that, when we

  • Modified VLSI designs for error correction codes

    Creator:
    Chen, Lupin
    Abstract:
    Nowadays, error correction codes have become an integral part in almost all the modern digital communication and storage systems. With the continuously increasing demands for higher speed and lower power communication systems, efficient VLSI implementations of those error correction codes have great importance for practical applications. In this thesis, several...
    Resource Type:
    Masters Thesis
    Full Text:
    my major professor, Dr. Zhongfeng Wang. I feel very honored and privileged to have worked under his

  • TIMR : Time Interleaved Multi Rail

    Creator:
    Ruggeri, Thomas L.
    Abstract:
    This work presents a new energy saving technique for modern digital designs. We propose Time Interleaved Multi-Rail (TIMR) - a method for providing two dynamic supply rails to a circuit. This technique uses the first supply rail to mask the transition delay while changing the voltage of the second rail....
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    Masters Thesis
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    path of finite resistance from the supply to ground. This finite resistance is very large, but it is