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  • Compatible field-effect and bipolar transistors

    Creator:
    Cheung, David Kin-Poon
    Abstract:
    Four methods for the simultaneous fabrication of field-effect and bipolar transistors have been investigated. The basic process involves obtaining two different junction depths by a single diffusion. This was accomplished by the techniques of (1) partial masking, (2) two depositions, (3) etched channels, and (4) oxide depletion. The first three...
    Resource Type:
    Masters Thesis
    Full Text:
    predictability. The field-effect transistor parameters obtained were comparable for all three methods

  • A MOS-transistor with submicron, and graded channel

    Creator:
    Chou, Pen Chao
    Abstract:
    The theoretical aspects and fabrication techniques of a new surface field-effect transistor were investigated. The new MOS-transistor uses a three-layer structure similar to those found in bipolar transistors. The new MOS structure introduces an impurity gradient in the channel region of the transistor and also makes it possible to reduce...
    Resource Type:
    Dissertation
    Full Text:
    A MOS-transistor with submicron, and graded channel AN

  • The MOS tetrode transistor

    Creator:
    Limvorapun, Thawee
    Abstract:
    The MOS tetrode transistor is studied in this project. This device is ideally suited for high frequency and switching application. In effect it is the solid state analogy of a multigrid vacuum tube performing a very useful multigrid function. A new structure is developed for p-channel 10 ohm-cm. silicon substrate...
    Resource Type:
    Masters Thesis
    Full Text:
    The MOS tetrode transistor AN ABSTRACT OF THE THESIS OF

  • A complementary MOS random-access-memory cell wth double-diffused MOS transistors

    Creator:
    Tao, David Ming-Shih
    Abstract:
    The use of double-diffused n-type MOS transistor (DN-MOS) in a complementary MOS random-access-memory (CMOS RAM) cell is the main objective of this investigation. DN-MOS transistors and conventional p-channel MOS transistors on the same chip have been successfully fabricated. Process sequence effects on device threshold voltage and channel length are discussed....
    Resource Type:
    Dissertation
    Full Text:
    transistor (W-MOS) in a complementary MOS random-access-memory (CMOS RAM) cell is the main objective of

  • Transistor circuit design for optimum noise performance

    Creator:
    Wilkerson, John Lee
    Resource Type:
    Masters Thesis
    Full Text:
    Transistor circuit design for optimum noise performance

  • Transistor DC amplifier design theory

    Creator:
    McGowan, Gerald Frank
    Resource Type:
    Masters Thesis
    Full Text:
    Transistor DC Amplifier Design Theory TR.NSISTOR DC At

  • The field-effect transistor as a medium-speed, low-level chopper

    Creator:
    Rux, Peter Turner
    Resource Type:
    Masters Thesis
    Full Text:
    -EFF ECT TRANSISTOR AS A MEDIUM-SPEED LOW-LEVEL CHOPPER Abstract approved (Major prof es sor) The

  • Predicting transistor switching time

    Creator:
    Richardson, Dennis W.
    Abstract:
    This thesis is a development of two sets of equations predicting the switching times of a saturated transistor. The first set of equations defines the rise, storage, and fall times at a single operating point where the transistor beta, cutoff frequency and collector capacitance are known. The second set of...
    Resource Type:
    Masters Thesis
    Full Text:
    predicting the switching times of a saturated transistor. The first set of equations defines the rise

  • A method for analysis of direct-coupled transistor amplifiers

    Creator:
    Bishop, Stanley Robert
    Abstract:
    The demand for transistor circuitry to perform within more exacting specifications has created the need for a method to accurateIy predict transistor circuit performance. A method utilizing an electronic digital computer for the analysis of direct-coupled transistor amplifiers is explained in this paper. The dc bias levels and the mid-band...
    Resource Type:
    Masters Thesis
    Full Text:
    ANALYS$ OF DIRECT-COUPLED Abstract approved aJor pro The dernand for transistor circuitry to perforrn

  • Majority logic circuits

    Creator:
    Anand, Satish Kumar
    Abstract:
    This thesis considers the worst-case design of transistor circuits for the realization of Majority Logic. First the meaning of Majority Logic is discussed. The requirement of an odd number of inputs for the realization of Majority Logic is justified. The usefulness of Majority Logic in synthesizing a Boolean expression is...
    Resource Type:
    Masters Thesis
    Full Text:
    thesis considers the worst -case design of transistor circuits for the realization of Majority Logic