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  • An alternative architecture for performing basic computer arithmetical operations

    Creator:
    Djang, Kevin
    Abstract:
    The arithmetic portions of almost all modern processor architectures are of very similar design. We use the term "traditional" to describe this design, the primary characteristics of which are native support for integer and floating-point number types and special disjoint instructions and hardware for each supported type. Decades of refinement...
    Resource Type:
    Masters Thesis
    Full Text:
    An alternative architecture for performing basic computer

  • The dynamic simultaneous multithreaded processor

    Creator:
    Ortiz-Arroyo, Daniel
    Abstract:
    This dissertation investigates diverse techniques to support multithreading in modern high performance processors. The mechanisms studied expand the architecture of a high performance superscalar processor to control efficiently the interaction between software-controlled and hardware-controlled multithreading. Additionally, dynamic speculative mechanisms are proposed to exploit thread-level-parallelism (TLP) and instruction-level-parallelism (ILP) on a...
    Resource Type:
    Dissertation
    Full Text:
    4.1 Simulation Tools in Computer Architecture

  • Development and evaluation of X32V

    Creator:
    Hong, Jumnit
    Abstract:
    Embedded processors are utilized in many applications with considerable time spent developing and maintaining functionality and performance. Performance being a key factor in adding features such as video and audio to a product. Configurable processors, such as X32V, allow the addition of functionality and performance without large increases in design...
    Resource Type:
    Masters Thesis

  • The dynamic speculation and performance prediction of parallel loops

    Creator:
    Zier, David A.
    Abstract:
    General purpose computer systems have seen increased performance potential through the parallel processing capabilities of multicore processors. Yet this potential performance can only be attained through parallel applications, thus forcing software developers to rethink how everyday applications are designed. The most readily form of Thread Level Parallelism (TLP) within any...
    Resource Type:
    Dissertation
    Full Text:
    in Electrical and Computer Engineering presented on May 1, 2009. Title: The Dynamic Speculation and

  • Investigating new design alternatives for a radix-2 modular multiplier kernal and I/O subsystem

    Creator:
    Chaitheerayanon, Akekalak
    Abstract:
    A main arithmetic operation for cryptographic systems is modular exponenti- ation. Exponentiation is computed by a long sequence of modular multiplications. Modular multiplication can be implemented in a general-purpose processor or a dedicated hardware, but dedicated hardware tends to be faster than a processor. Modular multiplication is a time-consuming operation,...
    Resource Type:
    Masters Thesis
    Full Text:
    for the degree of Master of Science in Electrical & Computer Engineering presented on December 16

  • Single-level dynamic register caching architecture for high-performance superscalar processors

    Creator:
    Liebert, John A.
    Abstract:
    The amount of instruction level parallelism (ILP) that can be exploited depends greatly on the size of the instruction window and the number of in-flight instructions the processor can support. However, this requires a register file with a large set of physical registers for renaming and multiple ports to provide...
    Resource Type:
    Masters Thesis
    Full Text:
    and Computer Engineering presented on September 21, 2006. Title: Single-Level Dynamic Register

  • Optimizing the advanced encryption standard on Intel's SIMD architecture

    Creator:
    Godbole, Pankaj
    Abstract:
    The Advanced Encryption Standard (AES) is the new standard for cryptography and has gained wide support as a means to secure digital data. Hence, it is beneficial to develop an implementation of AES that has a high throughput. SIMD technology is very effective in increasing the performance of some cryptographic...
    Resource Type:
    Masters Thesis
    Full Text:
    Master of Science in Electrical and Computer Engineering presented on January 15, 2004. Title

  • Fast data replenishment in peer to peer networks

    Creator:
    Dhamodaran, Arul Nambi
    Abstract:
    Peer-to-Peer (P2P) based distributed storage systems have gain much popularity in recent years. These systems rely greatly on the data redundancy to be robust under network dynamics, i.e., the dynamics of peer entering and departing the network. Hence, it is important to implement mechanisms for maintaining a certain level of...
    Resource Type:
    Masters Thesis
    Full Text:
    degree of Master of Science in Electrical and Computer Engineering presented on September 12, 2011

  • Modeling and dynamics analysis of P2P networks based on evolutionary games

    Creator:
    Cho, Seungyun
    Abstract:
    Since free riders in P2P network reduce the system's performance, how to maintain and encourage the nodes' cooperation is an important aspect of P2P related research. In this thesis, a P2P system is modeled based on two games: stag hunt game and snowdrift game. To relate the model to the...
    Resource Type:
    Masters Thesis
    Full Text:
    AN ABSTRACT OF THE THESIS OF Seungyun Cho for the degree of Master of Science in Computer Science

  • Optimizing performance/watt of embedded SIMD multiprocessors through a priori application guided power scheduling

    Creator:
    Albright, Ryan K.
    Abstract:
    A method for improving performance/watt of an embedded single-instruction multiple-data (SIMD) architecture using application-guided a priori scheduling of hardware resources is presented. A multi-core architectural simulator is adopted that accurately estimates power, performance, and utilization of various processor components (logic, interconnect and memory). A greedy search is then performed on...
    Resource Type:
    Masters Thesis
    Full Text:
    degree of Master of Science in Electrical and Computer Engineering presented on April 20, 2012. Title