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Filtering by: Creator Chang, C.-H. Remove constraint Creator: Chang, C.-H. Subject Analog-to-digital converters Remove constraint Subject: Analog-to-digital converters

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  • Error canceling low voltage SAR-ADC

    Creator:
    Wen, Jianping
    Abstract:
    The design of a switched capacitor successive approximation A/D converter is discussed in this thesis. This design adopts a novel capacitance mismatch error cancellation algorithm proposed in references [25, 27]. Detailed charge domain analysis is given in this thesis, which results in an improvement of the proposed algorithm by tracing...
    Resource Type:
    Masters Thesis
    Full Text:
    (c) Ci1 CID EH( H( )H- +Vri V1 +V, '' c1 C52 IC,p Cr2,, ± C Switch setting 2 (b) C51,, Crip

  • Generalized radix design techniques for low-power, low voltage pipelined and cyclic analog-digital converters

    Creator:
    Sharma, Vivek
    Abstract:
    This thesis proposes a novel technique for the design of pipelined and cyclic ADCs utilizing generalized radix gain stages. Several models have been proposed for the optimization of high performance pipelined ADCs by various researchers. This work builds upon them, using a simple but accurate model to estimate the optimal...
    Resource Type:
    Masters Thesis
    Full Text:
    Cyclic Analog-Digital Converters. Abstract approved: Gabor C. Temes and Un-Ku Moon This thesis

  • Low power design techniques for analog-to-digital converters in submicron CMOS

    Creator:
    Musah, Tawfiq
    Abstract:
    Advances in process technologies have led to the development of low-power high speed digital signal processing blocks that occupy small areas. These advances are critical in the development of portable electronic devices with small feature size and long battery life. However, the design of analog and mixed-signal building blocks, especially...
    Resource Type:
    Dissertation
    Full Text:
    21 A 1 C H R o2 Φ 2 G m2 R o2 Φ 22 V OUT C F C S Φ 1 Φ 2 V IN Φ 1 Φ 1

  • Linearizing techniques for voltage controlled oscillator based analog to digital converters

    Creator:
    Rao, Sachin B.
    Abstract:
    Voltage controlled oscillator (VCO) based ADC is an important class of time-domain ADC that has gained widespread acceptance due to their several desirable properties. VCO-based ADCs behave like an open-loop continuous time ΔΣ modulator and achieve excellent resolution by first order noise shaping the quantization error. However, the SNDR of...
    Resource Type:
    Dissertation
    Full Text:
    divider. (c) Frequency detector. . . . . . . . . . 73 5.11 Schematic of 1-bit ∆Σ DAC

  • Design techniques for time based data converters

    Creator:
    Gande, Manideep
    Abstract:
    Modern day CMOS processes are characterized by voltage scaling and geometry scaling. Geometry scaling helps reduce gate delays, thereby aiding in the design of data converters which use time based processing. Another artifact of geometry scaling is the increase in complexity of digital circuitry available on traditional analog ICs, as...
    Resource Type:
    Dissertation
    Full Text:
    members Prof. Karti Mayaram, Prof. Gabor C. Temes, and Prof. Pavan Kumar Hanumolufor for serving on my

  • Design of high-performance pipeline analog-to-digital converters in low-voltage processes

    Creator:
    Myers, Charles Grant
    Abstract:
    Pipeline analog-to-digital converters (ADCs) have long been used in high-speed systems for power-efficient data conversion. Broadband communication and video processing systems are placing high demands on converter accuracy and speed (above 14 bits and in the multiple-MHz range). The increasing converter requirements coupled with lower supply voltages in modern processes...
    Resource Type:
    Masters Thesis
    Full Text:
    . Fundamental barriers to an economical solution at this accuracy level, such as kT/C thermal noise, are

  • Techniques for improving timing accuracy of multi-gigahertz track/hold circuits

    Creator:
    Wang, Jingguang
    Abstract:
    Multi-Gigahertz sampling rate Analog-to-Digital Converters (ADC) with 5-8 bits resolution are used in many signal communication applications. Unfortunately, the performance of the high speed ADC is limited by the timing accuracy of the sampling clock. A small sampling uncertainty can cause a large error in the sampled voltage and result...
    Resource Type:
    Masters Thesis
    Full Text:
    . For different architectures of the T/H circuits, the timing error can arise from the clock random

  • Time and statistical information utilization in high efficiency sub-micron CMOS successive approximation analog to digital converters

    Creator:
    Guerber, Jon
    Abstract:
    In an industrial and consumer electronic marketplace that is increasingly demanding greater real-world interactivity in portable and distributed devices, analog to digital converter efficiency and performance is being carefully examined. The successive approximation (SAR) analog to digital converter (ADC) architecture has become popular for its high efficiency at mid-speed and...
    Resource Type:
    Dissertation
    Full Text:
    ...................................................................................................... 128 6.3.3 C-R2R DAC Optimization

  • 20-stage pipelined ADC with radix-based calibration

    Creator:
    Yun, Chong Kyu
    Abstract:
    A radix-based calibration technique was previously proposed with a two-stage algorithmic analog-to-digital converter (ADC). The objective of this work is to verify the capability of radix-based calibration for a true multi-stage ADC. In order to prove the idea, a single bit-per-stage, 20-stage pipelined ADC is designed in a 0.35-μm CMOS...
    Resource Type:
    Masters Thesis
    Full Text:
    subjects in the analog field. Thanks to Dong-Young Chang for helping me start in the beginning of the

  • OP-AMP free SC biquad LPF and delta-sigma ADC

    Creator:
    Yoo, Kiseok
    Abstract:
    The objective of this work is to explore the feasibility of replacing conventional op-amps with inverters in switched-capacitor (SC) circuits. In order to verify the idea, a low-pass filter (LPF) and a second-order delta-sigma (∆Σ) analog-todigital converter (ADC) are designed in the 0.5-m CMOS technology. The low-pass filter structure is...
    Resource Type:
    Masters Thesis
    Full Text:
    deviation due to channel charge is Vout Vin CK CH 15 H THinDDox C VVVWLC V 2