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Filtering by: Creator Osozawa%2C S. Remove constraint Creator: Osozawa%2C S. Subject Analog-to-digital converters Remove constraint Subject: Analog-to-digital converters

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  • Low-voltage pipeline A/D converter

    Creator:
    Wu, Lei
    Abstract:
    Continuous process scale-down and emerging markets for low-power/low-voltage mobile systems call for low-voltage analog integrated circuits. Switched-capacitor (SC) circuits are the building blocks for analog signal processing and will encounter severe overdrive problems when operating at low voltage conditions. There exist three techniques to solve the problem, but with their...
    Resource Type:
    Masters Thesis
    Full Text:
    scheme over the switched-opamp technique, a 10-bit 20 MS/s pipeline A/D converter operating at 1.5 V

  • Design of high-performance pipeline analog-to-digital converters in low-voltage processes

    Creator:
    Myers, Charles Grant
    Abstract:
    Pipeline analog-to-digital converters (ADCs) have long been used in high-speed systems for power-efficient data conversion. Broadband communication and video processing systems are placing high demands on converter accuracy and speed (above 14 bits and in the multiple-MHz range). The increasing converter requirements coupled with lower supply voltages in modern processes...
    Resource Type:
    Masters Thesis
    Full Text:
    improved signal power and sample-and-hold (S/H) removal for noise and power savings. The presented

  • Compensation method of the excess loop delay in continuous-time delta-sigma ADCs based on model matching approach

    Creator:
    Guo, Jia
    Abstract:
    Continues-Time (CT) Delta-Sigma (ΔΣ) Analog-to-Digital Converters (ADCs) have one important constrain, namely the excess loop delay. Most previous excess lop delay compensation methods need to know the exact value of the excess loop delay in advance. However, the value of the excess loop delay is a uniformly distribution random variable....
    Resource Type:
    Masters Thesis
    Full Text:
      .......................................................... 55  Figure 5.4 CT ΔΣ ADC block diagram with compensators 1C and 2C ......................... 55

  • Time and statistical information utilization in high efficiency sub-micron CMOS successive approximation analog to digital converters

    Creator:
    Guerber, Jon
    Abstract:
    In an industrial and consumer electronic marketplace that is increasingly demanding greater real-world interactivity in portable and distributed devices, analog to digital converter efficiency and performance is being carefully examined. The successive approximation (SAR) analog to digital converter (ADC) architecture has become popular for its high efficiency at mid-speed and...
    Resource Type:
    Dissertation

  • Novel structures for high-speed delta-sigma data converters

    Creator:
    Chae, Jeong Seok
    Abstract:
    As CMOS processes keep scaling down devices, the maximum operating frequencies of CMOS devices increase, and hence circuits can process very wide band signals. Moreover, the small physical dimensions of transistors allow the placing of many more blocks into a single chip, including highly accurate analog blocks and complicated digital...
    Resource Type:
    Dissertation
    Full Text:
    . 9 0.5 0.6 0.7 0.8 0.9 1 52 54 56 58 60 62 64 66 k S N D R [d B ] Figure 2.5: Peak

  • Wide-bandwidth, high-resolution delta-sigma analog-to-digital converters

    Creator:
    Zanbaghi, Ramin
    Abstract:
    There is a significant need in recent mobile communication and wireless broadband systems for high-performance analog-to-digital converters (ADCs) that have wide bandwidth (BW>5-MHz) and high data rate (>100-Mbps). A delta-sigma ADC is recognized as a power-efficient ADC architecture when high resolution (>12-b) is required. This is due to several advantages...
    Resource Type:
    Dissertation
    Full Text:
    : ______________________________________________________ Terri S. Fiez There is a significant need in recent mobile communication

  • Design and analysis techniques for nano-joule ADCs and sampling linearity

    Creator:
    Brown, Thomas (Thomas William)
    Abstract:
    Two aspects of ADC system performance are addressed in this work. First, the combination of the ADC and its associated reference are co-designed for an energy constrained remote sensing system. Second, sampling linearity is mathematically analyzed as a function of frequency to provide enhanced understanding into an ADC's requisite sampling...
    Resource Type:
    Dissertation
    Full Text:
    : Design and Analysis Techniques for Nano-Joule ADCs and Sampling Linearity Abstract approved: Terri S

  • High efficiency wideband low-power delta-sigma modulators

    Creator:
    Lee, Sang Hyeon
    Abstract:
    Delta-sigma analog-to-digital converters traditionally have been used for low speed, high resolution applications such as measurements, sensors, voice and audio systems. Through continued device scaling in CMOS technology and architectural and circuit level design innovations, they have even become popular for wideband, high dynamic range applications such as wired and...
    Resource Type:
    Dissertation
    Full Text:
    -50 0 Frequency , f / f s P S D , d B signal band edge integrated noises 1st-order

  • Compensation techniques for cascaded delta-sigma A/D converters and high-performance switched-capacitor circuits

    Creator:
    Sun, Tao
    Abstract:
    This thesis describes compensation techniques for cascaded delta-sigma A/D converters (ADCs) and high-performance switched-capacitor (SC) circuits. Various correlated-double-sampling (CDS) techniques are presented to reduce the effects of the nonidealities, such as clock feedthrough, charge injection, opamp input-referred noise and offset, and finite opamp gain, in SC circuits. A CDS technique...
    Resource Type:
    Dissertation
    Full Text:
    , such as comparators, voltage amplifiers, sample-and-hold (S/H) stages and integrators, etc. 2.2 The

  • Digital implementation of a mismatch-shaping successive-approximation ADC

    Creator:
    Coe, Matthew T.
    Abstract:
    Utilizing a two-capacitor topology, the digital implementation of an audio-band successive-approximation analog-to-digital converter (ADC) is explored in the context of mismatch-shaping where the mismatch estimates are accurate to the first order. A second-order Δ∑ loop was found to be effective in system simulations given a 0.1% capacitor mismatch. Spectral analysis...
    Resource Type:
    Masters Thesis
    Full Text:
    ) Q,ci = (Qo/8)(1 a) = (Qo/2)(1 Q3,c2 = (Qo/8)(1 - 3a) Q3,cl = (Qo/8)(1 + a) QC2 (Qo/4)(1 - 2a) S S