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  • Design of a 80/250-Msample/s FIR-filter for a pipelined ADC-FIR interface

    Creator:
    Stier, Hubert J.
    Resource Type:
    Masters Thesis
    Full Text:
    Master of Science in Electrical and Computer Engineering presented on May 3, 1995. Title: Design of a 80

  • High speed digital FIR filter design

    Creator:
    Zhou, Bo
    Abstract:
    The objective of this thesis is to design a high speed digital FIR filter. The inputs of the system come from a Delta-Sigma modulator. This FIR filter takes 1024 inputs, multiplies them with their coefficients and adds the results. The main design task is to take the input data, which...
    Resource Type:
    Masters Thesis
    Full Text:
    elegant way. Thanks to Westinghouse Electric Co. for their financial support on the project. And

  • Low noise FSCL digital circuits for decimation filter

    Creator:
    Wong, Man Wa
    Abstract:
    A new circuit technique called Folded Source Coupled Logic (FSCL) has been developed to implement the digital section of mixed-signal IC applications. This FSCL circuit technique offers the advantage of low overlap current spikes during the switching transitions of conventional CMOS gates. This overlap current spike has become one of...
    Resource Type:
    Masters Thesis
    Full Text:
    filter 42 LIST OF TABLES Table Page 1 Comparison of a 4-bit CLA and 4-bit CSA 16 2 Design

  • Sensitivity analysis and architectural comparison of narrow-band sharp-transition digital filters

    Creator:
    Kulkarni, Satish S.
    Abstract:
    Due to advances in high-density low-cost VLSI and communication technology, digital filtering and signal processing are being widely used for real-time signal processing applications. Given the filter specification, choosing the best filter structure for a given application is not a trivial task. The choice of a particular filter structure depends...
    Resource Type:
    Masters Thesis
    Full Text:
    digital structures which are based on LC lattice and ladder filters, respectively. 24 The design of

  • VLSI implementation of adaptive BIT/serial IIR filters

    Creator:
    Badyal, Rajeev
    Abstract:
    A new structure for the implementation of bit/serial adaptive IIR filter is presented. The bit level system consists of gated full adders for the arithmetic unit and data latches for the data path. This approach allows recursive operation of the IIR filter to be implemented without any global interconnections, minimal...
    Resource Type:
    Masters Thesis
    Full Text:
    communication and control structures of these arrays offer a substantial advantage for the VLSI design and