Current multi-gigahertz ADC performance is
limited by the sampling clock timing jitter. This paper describes
the effects of clock transition time on the spurious-free dynamic
range (SFDR) of a CMOS T/H circuit. A signal-dependent
nonlinearity model is first introduced that provides insight on the
effect of finite clock transition time,...
Various applications like wireless UWB communication, fast data acquisition systems and digital storage oscilloscopes needs ADCs with instantaneous input signal bandwidth from 0.1-40 GigaHertz range with 6-10 bits of resolution -- a challenging task and an impressive goal to achieve. Flash ADCs have been conventionally employed to achieve these goals...
Hand-held devices are among the most successful consumer electronics in modern society. Behind these successful devices, lies a key analog design technique that involves high-performance analog-to-digital conversion combined with very low power consumption. This dissertation presents two different approaches to achieving high power efficiency from a two-step pipelined architecture, which...
Analog-to-digital converters (ADCs) convert analog
continuous time signals into discrete time, digital format. One
precondition that must be met for conventional nyquist rate ADCs is
that the input signal must be suitably band-limited to an input
bandwidth less than the nyquist frequency. This mandates expensive
anti-alias filters which contribute to...
Two aspects of ADC system performance are addressed in this work. First, the combination of the ADC and its associated reference are co-designed for an energy constrained remote sensing system. Second, sampling linearity is mathematically analyzed as a function of frequency to provide enhanced understanding into an ADC's requisite sampling...
The design of a switched capacitor successive approximation A/D converter is discussed in this thesis. This design adopts a novel capacitance mismatch error cancellation algorithm proposed in references [25, 27]. Detailed charge domain analysis is given in this thesis, which results in an improvement of the proposed algorithm by tracing...
VCO-based ADCs have recently emerged as attractive alternative to conventional DeltaSigma (ΔΣ) modulator architectures. Few salient features of a VCObased ADC are: 1) the quantization noise is 1st order noise shaped, 2) it is an open loop architecture, and, 3) its implementation is mostly digital in nature. Hence, they are...
This dissertation presents an incremental analog-to-digital converter (ADC) with digital digital-to-analog converter (DAC) mismatch correction. A theoretical time-domain analysis technique was developed to predict the noise performance of the incremental ADC, and a new optimization technique was proposed to minimize the output noise.
In the calibration mode, the incremental ADC...
The purpose of the thesis is to synthesize the major results of a continuous
research effort directed toward new applications of high speed sampling in general and Electrooptic Sampling in particular.
Equivalent time sampling of repetitive high speed signals continues to provide significant performance enhancements for present and future generations...
The objective of this work is to explore the feasibility of replacing conventional op-amps with inverters in switched-capacitor (SC) circuits. In order to verify the idea, a low-pass filter (LPF) and a second-order delta-sigma (∆Σ) analog-todigital converter (ADC) are designed in the 0.5-m CMOS technology. The low-pass filter structure is...