This research work focuses on the mechanism of 1/f noise in GaAs
resistors on semi-insulating substrates and 1/f noise due to temperature
fluctuations in heat conduction in resistors, diodes, and bipolar transistors. The
goal of this research is to generate accurate models to explain physical origin of 1/f
noise in...
A circuit designed to generate and maintain a constant magnetic
flux is presented by using a sample-data control system, instead of a
continuous control system.
A Hall generator is used as the magnetic sensing element, and
is operated with a pulse bias to allow a large output. The output of...
Various applications like wireless UWB communication, fast data acquisition systems and digital storage oscilloscopes needs ADCs with instantaneous input signal bandwidth from 0.1-40 GigaHertz range with 6-10 bits of resolution -- a challenging task and an impressive goal to achieve. Flash ADCs have been conventionally employed to achieve these goals...
An analysis of substrate noise coupling in mixed-signal circuits has been performed in the TSMC 0.25 [mu]m lightly doped and heavily doped CMOS processes. Methods to minimize noise coupling in both the chip design and board design phases are presented along with techniques for accurate circuit simulation of noise coupling....
Three types of low noise amplifiers operating at 2.4GHz were designed. They are the commonly used single-ended and differential amplifiers as well as a new quasi-differential amplifier. The substrate noise injected into these amplifiers is examined for both heavily and lightly doped CMOS substrates. For the single-ended amplifier the noise...
We present a new circuit design for adaptive offset cancellation in a fully differential 2.4 GHz CMOS direct conversion mixer. Our circuit structure is a modification of a Gilbert cell mixer in which offsets are cancelled by injecting cancellation currents into the legs of the mixer by dynamically varying the...
This dissertation presents a dual-path 2-0 MASH (Multi-stAge-noise -SHaping) ADC with two verified digital corrections of DAC mismatch error and quantization noise leakage. By using these two techniques, the requirements for the analog circuits are greatly relaxed. The dual-path structure generates two outputs, one only composed of conversion errors, the...
A methodology for rapid estimation of substrate noise generated by digital circuitry in mixed-signal circuits is presented. This methodology is incorporated into the Silencer! framework, and also provides for future improvements including pre-layout noise estimation. Measurements of a test chip fabricated in the TSMC o.25[mu]m heavily doped logic process validate...
Digital phase-locked loops (PLLs) have been receiving increasing attention recently due to their ease of integration, scalability and performance comparable to their analog counterparts. In digital PLLs, increased resolution in time-to-digital conversion is desirable for improved noise performance. This work describes the design and simulation of a stochastic time-to-digital converter...