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Integrated circuits -- Very large scale integration
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VLSI design methodologies and computer tools
Acceleration of a heuristic PLA product term reduction program through complementation...
The architecture and design of a parallel sorting engine
The analysis and synthesis of a parallel sorting engine
Mapping of recursive algorithms onto multi-rate arrays
Time domain electromagnetic simulation of VLSI interconnects
Application and analysis of CMOS FSCL for mixed-mode analog/digital ICs
Design of complex digital blocks using folded source-coupled logic for mixed-mode appl...
Analysis and applications of layered multiconductor coupled slot and strip-slot struct...
Fully efficient pipelined VLSI arrays for solving toeplitz matrices
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Academic Affiliation
Electrical and Computer Engineering
11
Electrical Engineering and Computer Science
5
Advisor
Kiaei, Sayfe
4
Wang, Zhongfeng
4
Murray, John M.
2
Chiang, Patrick Y.
1
Liu, Huaping
1
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Commencement Year
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Commencement Year range end
Current results range from
1985
to
2012
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Committee Member
Liu, Huaping
3
Bose, Bella
2
Lee, Ben
2
Plant, Thomas K.
2
Chiang, Patrick
1
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Creator
Ahn, Byoungchul
1
Bate, John G.
1
Chen, Lupin
1
Chow, Andrew Siv Anne
1
Cui, Zhiqiang
1
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Current results range from
1985
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2012
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Decade
2010-2019
2
2000-2009
3
1990-1999
7
1980-1989
4
Degree Field
Electrical and Computer Engineering
16
Degree Level
Master's
10
Doctoral
6
Degree Name
Master of Science (M.S.)
10
Doctor of Philosophy (Ph.D.)
6
File Format
application/pdf
3
Language
English [eng]
16
License
All rights reserved
5
Non-Academic Affiliation
Oregon State University. Graduate School
16
Peer Reviewed
No
15
Resource Type
Masters Thesis
10
Dissertation
6
Rights Statement
Copyright Not Evaluated
10
In Copyright
6
Subject
Integrated circuits -- Very large scale integration
13
Decoders (Electronics)
2
Digital integrated circuits
2
Error-correcting codes (Information theory)
2
Integrated circuits -- Very large scale integration -- Design and construction -- Mathematical models
2
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