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  • The Architecture of a Reusable Built-In Self-Test for Link Training, IO and Memory Defect Detection and Auto Repair on 14nm Intel SOC

    Creator:
    Querbach, Bruce
    Abstract:
    The complexity of designing and testing today's system on chip (SOC) is increasing due to greater integrated circuit (IC) density and higher IO and memory frequencies. SOCs for the mobile phone and tablet market have the unique challenge of short product development windows, at times less than six months, and...
    Resource Type:
    Dissertation
    Full Text:
    Querbach for the degree of Doctor of Philosophy in Electrical and Computer Engineering presented on June

  • The GALAXY memory system

    Creator:
    Looney, James Chester
    Abstract:
    The GALAXY computer is a large, high speed, general purpose, digital computer intended to be used for solving scientific problems. It requires a random access memory system of 16,384 words of 59 bits each with a cycle time of one microsecond or less. A memory system capable of meeting these...
    Resource Type:
    Masters Thesis
    Full Text:
    . Fundamental Investigation of Digital Computer Storage and Access Techniques. Menlo Park, California, Stanford

  • Design and evaluation of a glass delay line content-addressable memory system

    Creator:
    Rux, Peter Turner
    Abstract:
    The high cost of content-addressed memories (CAM) can be reduced significantly by using a circulating memory system. With the circulating system, comparison logic is shared by many memory locations to allow a reduction in cost. Three data organizations are described and evaluated and one is chosen as the best for...
    Resource Type:
    Dissertation
    Full Text:
    Capabilities of a Content-Addressable Memory Most present-day computer memories are information storage

  • The effect of both hardware and software parameters on the efficiency of a paging system

    Creator:
    Frank, Rudolph Joseph
    Abstract:
    Due to the present trend to utilize both virtual memory and paging for the implementation of storage for large-scale computer systems, it is of interest to analyze the pertinent parameters associated with the operation of a paging system. This paper describes the paging process and determines the effect of variations...
    Resource Type:
    Masters Thesis
    Full Text:
    utilize both virtual memory and paging for the implementation of storage for large-scale computer

  • Priority structures for multiaccess memory systems

    Creator:
    Hill, James Carver
    Abstract:
    The quest for greater computer-system speed has brought about a continuing increase in the parallelism of these systems. In particular, the number of processors and other devices which are required to access the same core-memory not for economy, but for the advantages to be derived from using the memory as...
    Resource Type:
    Dissertation
    Full Text:
    approved Redacted for Privacy e) Professor L. N. Stone The quest for greater computer-system speed has

  • Low power, high performance pseudo-static D flip-flop

    Creator:
    Low, Tim D.
    Abstract:
    Digital systems, in particular microprocessor, have recently experienced phenomena growth in performance. Both technology advancement and clever design have sustained this performance growth. As clock frequency heads into the Ghz range, new circuit design, for both logic and storage, are needed. Such new circuit technology must provide needed performance with...
    Resource Type:
    Masters Thesis
    Full Text:
    " case, the flip-flop has difficulty storing a charge. Due to the storage limitation of the device, the

  • Tolerating processor-memory performance gap

    Creator:
    Lai, Shih-Chang
    Abstract:
    While the performance gap between microprocessors and main memory is ever increasing each year, cache memory has been a bridge to alleviate this discrepancy. In this thesis proposal, we introduce three techniques to tolerate this processor and memory speed imbalance. First, we propose the bloom filter scheme to identify which...
    Resource Type:
    Dissertation
    Full Text:
    degree of Doctor of Philosophy in Electrical and Computer Engineering presented on October 31, 2002

  • Reduced instruction set computer memory architectures

    Creator:
    Widjaja, Stephen
    Abstract:
    This thesis describes the design of a Reduced Instruction Set Computer. Its instruction memory utilizes a unique cache architecture and a two-stage memory pipelining technique. Because of the bandwidth of the 64-bit instruction bus, instruction prefetching is possible and is implemented. The data memory is bridged by a four-way set-associative...
    Resource Type:
    Masters Thesis
    Full Text:
    Reduced instruction set computer memory architectures AN

  • Design and modeling of low-power register file memories

    Creator:
    Donkoh, Eric Kwesi
    Abstract:
    With the evolving popularity of new computing platforms such as Ultrabooks, Tablets, and Smart Phones, and the shift to multi-core computing, power is now the key performance limiter, a departure from the traditional frequency limitation. As such, increasingly low-power design solutions feature prominently in early architectural and design space exploration...
    Resource Type:
    Dissertation
    Full Text:
    and Computer Engineering presented on June 13, 2013. Title: Design and Modeling of Low-Power