A negatively biased substrate has several advantages over a grounded substrate in CMOS
technology. The on-chip generation of this negative substrate bias has made chips easier
to use when only a single supply is preferred. This project demonstrates two types of
charge pump circuits used to generate negative voltages not...
Herein, a program of research is detailed related to transport through the Si metal oxide semiconductor (MOS) quantum dots fabricated in a process flow compatible with modern ULSI (ultra large scale integrated circuit). Silicon quantum dots were fabricated by placing split gates within a MOSFET structure. Quantum dots of several...
All-digital PLLs promise flexible and precise frequency modulation continous-wave(FMCW) radar signal signal for 77GHz radar applications. Such PLLs require digitally-controlled oscillators(DCO) with wide frequency tuning range and high resolution to address a range of applications and low phase noise requirements. In this thesis, novel resonator structures with ne capacitance/inductance switching...
A MOS biquadratic (biquad) filter employing the switched-current technique is
reported. The circuit uses current-mode processing which can offer wide
bandwidth, low voltage operation, and can be implemented with standard CMOS
technology. Examples of lowpass, highpass, and bandpass filters are given
which illustrate the synthesis procedures and the versatility of...
With increasing interest in current-mode analogue processing due to its high
performance properties such as speed, bandwidth and accuracy compared to voltage-mode
processing, new current-mode alternatives to various conventional circuit designs are
appearing. In this report, a novel circuit design to construct a fully-differential current-mode
operational amplifier ( OP-AMP )...
This thesis describes the analysis and comparison of Folded Source-Coupled
Logic (FSCL) with standard static CMOS, cascode voltage-switch logic and differential
split-level logic gates. The advantages of FSCL are low switching noise and
high operating speed. The effect of voltage and device scaling on these topologies is
evaluated in terms...