Graduate Thesis Or Dissertation
 

Digital phase-locked loops for multi-GHz clock generation

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https://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/73666879r

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  • A digital implementation of a PLL has several advantages compared to its analog counterpart. These include easy scalability with process shrink, elimination of the noise susceptible analog control for a voltage controlled oscillator (VCO) and the inherent noise immunity of digital circuits. Several recent digital PLL (DPLL) implementations have achieved performance similar to that of analog PLLs. However, there is an upper bound on the bandwidth of a DPLL and this limits its capability to track an input signal. The research described in this thesis is focused on new digital PLL architectures that overcome this bandwidth limitation in linear as well as in digital PLLs. A systematic design procedure for a second-order digital phase-locked loop with a linear phase detector is proposed. The design procedure is based on the analogy between a type-II second-order analog PLL and a digital PLL. A new digital PLL architecture featuring a linear phase detector which eliminates the noise-bandwidth tradeoff is presented. It employs a stochastic time-to-digital converter (STDC) and a high frequency delta-sigma dithering to achieve a wide PLL bandwidth and a low jitter. The measured results obtained from the prototype chip demonstrate a significant jitter improvement with the STDC. A bang-bang digital PLL employing an adaptive tracking technique and a novel frequency acquisition scheme achieves a wide tracking range and fast frequency acquisition. The DPLL operates over a wide frequency range from 0.6GHz to 2GHz. The adaptive tracking mechanism detects PLL slewing by monitoring the output of the binary phase detector and corrects the VCO frequency to prevent loss of lock. The experimental results illustrate a tracking bandwidth improvement of 100%. As a result, this DPLL is suitable for applications employing spread-spectrum clocking. A fast frequency lock is achieved with a novel frequency detector which extracts the frequency error from the feedback divider in a PLL.
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