Graduate Thesis Or Dissertation
 

Design techniques for successive approximation register analog-to-digital converters

Public Deposited

Downloadable Content

Download PDF
https://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/ht24wn523

Descriptions

Attribute NameValues
Creator
Abstract
  • Successive approximation register analog-to-digital converters (SAR ADCs) have been widely used for medium-speed, medium-resolution applications due to their excellent power efficiency and digital compatibility. Recently, SAR ADCs are also penetrating into the applications which have been earlier dominated by delta-sigma ADCs and pipeline ADCs. However, the resolution of SAR ADCs is limited by component mismatch, and their speed is generally slow due to serial operation. In this work, several system innovations and design techniques are investigated for SAR ADCs. First, a semi-synchronous clocking is proposed to optimize the comparator resolving time and DAC settling time in the SAR conversion. Simulations show a 40% speed-up compared with conventional synchronous processing. A self-calibration technique to correct the capacitor mismatch error is also introduced. The proposed calibration algorithm is verified to be insensitive to the non-idealities in the calibration DACs.
License
Resource Type
Date Available
Date Issued
Degree Level
Degree Name
Degree Field
Degree Grantor
Commencement Year
Advisor
Committee Member
Academic Affiliation
Non-Academic Affiliation
Rights Statement
Publisher
Peer Reviewed
Language
Replaces

Relationships

Parents:

This work has no parents.

In Collection:

Items

Thumbnail Title Date Uploaded Visibility Actions
file details TongTao2011.pdf 2017-08-15 Public Download