Processor memory traffic characteristics for on-chip cache Public Deposited

http://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/r781wj56v

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  • The motivation of this research is to study different cache designs for on-chip caches that improve processor performance and at the same time minimize the degradation to system performance caused by an increase in the processor memory traffic. As VLSI technology advances we can have bigger and more complex on-chip caches that could not have been possible a few years ago. Results derived from on-chip caches and performance issues are basically similar to off-chip caches. In this study, we will concentrate on single level on-chip caches though there are many interesting issues relating system performance, memory traffic and multi-level caches.
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  • description.provenance : Made available in DSpace on 2013-02-16T19:05:40Z (GMT). No. of bitstreams: 1 HoJeremyYuiLuen1992.pdf: 2990660 bytes, checksum: bb199880f9e7d464004d38c74fa56b56 (MD5) Previous issue date: 1992-04-16
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  • description.provenance : Approved for entry into archive by Patricia Black(patricia.black@oregonstate.edu) on 2013-02-16T19:05:40Z (GMT) No. of bitstreams: 1 HoJeremyYuiLuen1992.pdf: 2990660 bytes, checksum: bb199880f9e7d464004d38c74fa56b56 (MD5)

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