Multiprocessor computers with replicated shared memory Public Deposited

http://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/tx31qm684

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  • Multiprocessor computers may eventually be the only method of increasing computer throughout. One of the major problems with multiprocessor computers is the interference or contention between processors when accessing a shared resource. This work describes the design, construction, and analysis of a prototype multiprocessor computer utilizing a replicated shared memory for interconnection which has less interference than many conventional interconnection net works. The prototype multiprocessor computer consists of five processor boards and a communications board. Each processor board contains an Intel 8086 central processing unit (CPU), resident and shared random access memory (RAM), and associated control circuitry, The shared RAM consists of five copies (replication), one for each processor, with concurrent and independent read cycles and a common write cycle. Thus, this shared memory provides minimal interference for read operations. A general probabilistic model to predict throughput with interference for a system of N processors and M shared resources is developed. Input parameters for the model include the number of processors, number of shared resources, resource utilizations, processor priority, and bandwidth of the resources. This model is applied to replicated shared memory multiprocessor computers for systems of two to five processors, two to five shared memories, and shared memory utilizations of 5%, 10%, 15%, 20%, 25%, and 30% (per processor per shared memory). When compared to conventional shared uniport memory systems, the model predicts throughput improvements (speedup) of up to 400% for a system with five processors, one shared memory, memory utilization of 0.5, and a read utilization factor of 90%. Results of experiments conducted on the five-processor prototype computer agree to within 3.17% of results predicted by the model for utilizations 'below memory saturation' (total usage of memory less than 100%). Above memory saturation, the model over estimates throughput because of processor queueing that occurs on the actual machine. For the case with read interference (memory arbiter interference), an additional interference term was added to the model results. These model results agree to within 4.87% of experimental results.
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