Search Constraints

Start Over
Filtering by: Creator Birkemeier, W. A. Remove constraint Creator: Birkemeier, W. A. Academic Affiliation Electrical Engineering and Computer Science Remove constraint Academic Affiliation: Electrical Engineering and Computer Science Advisor Moon, Un Ku Remove constraint Advisor: Moon, Un Ku

Search Results

  • Investigation of a noise-shaping accelerometer interface circuit for two-chip implementation

    Creator:
    Zechmann, Jacob W.
    Abstract:
    The world market for sensors is several hundred million dollars growing at an annual rate of 20 percent with accelerometers comprising 19 percent of the market. With an increasing market, a wide range of applications with varying degrees of resolution are in demand. Therefore, there is sufficient motivation for developing...
    Resource Type:
    Masters Thesis
    Full Text:
    by Jacob W. Zechmann June 30, 2005 All Rights Reserved _j Investigation of a Noise-Shaping

  • A 10 bit algorithmic A/D converter for a biosensor

    Creator:
    Rengachari, Thirumalai
    Abstract:
    This thesis presents a novel algorithmic A/D converter to be used in a biosensor. The converter is capable of a conversion rate of 1.5 bits/phase and hence the required conversion time is reduced. The proposed architecture is analyzed for non-ideal effects and compared with existing algorithmic A/D architectures. The converter...
    Resource Type:
    Masters Thesis
    Full Text:
    . Title: A 10 Bit Algorithmic A/D Converter for a Bio-sensor Abstract approved: Gabor C. Temes and Un-Ku

  • A multi-bit hybrid DSM over full-scale range without feedback DEM

    Creator:
    Kwon, Sunwoo, 1974-
    Abstract:
    Evolution of the mobile communication standards and proliferation of hand-held devices mandate stringent Analog-to-Digital Converter (ADC) specifications. Among various ADCs, a ∆Σ ADC is best known as a power-efficient ADC when more than 12b is required. However, a conventional discrete-time (DT) ∆Σ Modulator (∆ΣM) is inadequate for low-power wideband applications...
    Resource Type:
    Dissertation
    Full Text:
    Doctor of Philosophy in Electrical and Computer Engineering presented on March 27, 2009. Title: A Multi

  • Characterization of a digital phase locked loop and a stochastic time to digital converter

    Creator:
    Geissenhainer, Erik D.
    Abstract:
    A digital phase locked loop (DPLL) and a statistical time-to-digital converter (STDC) were previously fabricated in a 0.35µm, 3.3V SOI CMOS process. This work summarizes these designs and characterizes the measured performance. Simulations supplement the measurements where applicable. The DPLL was found to reach a locked state under a limited...
    Resource Type:
    Masters Thesis
    Full Text:
    presented on July 21, 2006. Title: Characterization of a Digital Phase Locked Loop and a Stochastic

  • A multi-bit delta sigma audio digital-to-analog converter

    Creator:
    Wang, Ruopeng
    Abstract:
    Digital-to-analog converters (DACs) with wide dynamic range and high linearity are required for high-end audio applications. A multi-bit delta sigma audio DAC, using a novel gain-correction technique, is described in this thesis. For widely varying on-chip RC time constant, the DAC gain can be accurately controlled by the correction circuitry....
    Resource Type:
    Dissertation
    Full Text:
    of Philosophy in Electrical and Computer Engineering presented on June 5, 2006. Title: A Multi

  • Limitations and optimization of a blind calibration algorithm for nonlinearity in analog to digital converters

    Creator:
    Coker, Brandilyn
    Abstract:
    Analog to digital converters (ADCs) are a critical part of communication between the physical world and the increasingly digital systems humans use every day. ADCs have inherent non-idealities that degrade performance. Nonlinearity is one of the most prevalent non-idealities that designers face. While calibration methods for nonlinearity exist in the...
    Resource Type:
    Masters Thesis
    Full Text:
    third order calibration, a buffer of finite length Nbuff,finite is chosen such that there are w samples

  • A Wide Modulation Range and PVT-Tolerant Spread-Spectrum Modulation Clock Generator

    Creator:
    Sun, Hyuk
    Abstract:
    This dissertation presents a phase domain in-loop-bandwidth spread-spectrum clock generation technique. In this proposed technique, a charge-based discrete-time loop filter is proposed to enable the phase domain in-loop-bandwidth spread-spectrum modulation without a delta-sigma modulator or time-to-digital converter. The in-loop-bandwidth modulation technique maximizes the loop bandwidth to improve phase noise suppression...
    Resource Type:
    Dissertation
    Full Text:
    and Computer Engineering presented on December 8, 2016. Title: A Wide Modulation Range and PVT

  • A stochastic time-to-digital converter for digital phase-locked loops

    Creator:
    Ok, Kerem
    Abstract:
    Digital phase-locked loops (PLLs) have been receiving increasing attention recently due to their ease of integration, scalability and performance comparable to their analog counterparts. In digital PLLs, increased resolution in time-to-digital conversion is desirable for improved noise performance. This work describes the design and simulation of a stochastic time-to-digital converter...
    Resource Type:
    Masters Thesis
    Full Text:
    1980. [12] A. Marques, M. Steyaert and W. Sansen, “Theory of PLL fractional-N frequency synthesizers

  • A tunable duty-cycle-controlled switched-R-MOSFET-C CMOS filter for low-voltage and high-linearity applications

    Creator:
    Xiao, Ying
    Abstract:
    A novel switched-R-MOSFET-C input branch is proposed for low-voltage and high-linearity applications. The tunability is achieved by varying the clock duty cycle using an automatic tuning circuit. This tuning method does not involve a change in gate voltage, and is therefore particularly suitable for low-voltage applications. The advantages of the...
    Resource Type:
    Masters Thesis
    Full Text:
    , 2004 . Title: A Tunable Duty-Cycle-Controlled Switched-R-MOSFET-C CMOS Filter for Low-Voltage and

  • A fully digital technique for the estimation and correction of the DAC error in multi-bit delta sigma ADCs

    Creator:
    Wang, Xuesheng
    Abstract:
    This thesis proposes a novel fully digital technique for the estimation and correction of the DAC error in multi-bit delta sigma ADCs. The structure of the DAC error is indicated through a simple model for unit-element based DACs. The impact of the DAC error on the performance of ADC is...
    Resource Type:
    Dissertation
    Full Text:
    : A Fully Digital Technique for the Estimation and Correction of the DAC Abstract Error in Multi-bit