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Filtering by: Creator Caruso, B. A. Remove constraint Creator: Caruso, B. A. Academic Affiliation Electrical Engineering and Computer Science Remove constraint Academic Affiliation: Electrical Engineering and Computer Science Language English [eng] Remove constraint Language: English [eng]

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  • Three-Dimensional Network-on-Chip Architectures for Cycle Accurate Full-System Simulator

    Creator:
    Agarwal, Akash
    Abstract:
    High Performance Computing can find ubiquitous applications in the industry. HPC-applications are specifically designed to take advantage of the parallel nature of the computing systems which is often enabled by Multi-core/Many-core architectures. With this advent of Multi-processors in the mainstream systems, inter-core communication has been one of the major challenges...
    Resource Type:
    Presentation and Capstone Project
    Full Text:
    Network Routers 3D-Mesh NoC Designs. (A) 4x4x3 3D-Mesh (B) 2x2x2 3D-Mesh N x N x M 3D mesh = N * N

  • IC-Antenna Co-Integration for Efficient and Scalable Millimeter-Wave Antenna Interfaces

    Creator:
    Liu,Yao
    Abstract:
    Millimeter-wave (mm-wave) technology promises high speed, high system capacity and low latency interconnects with reduced cost. Applications like high data-rate wireless links, next generation automotive sensors and security body scanners highly depend on mm-wave technology innovations. As operating frequency moves to higher mm-wave bands, shrinking antenna dimensions enable co-integration of...
    Resource Type:
    Dissertation
    Full Text:
    . 2.1): (a) the digital baseband performing digital signal processing, (b) the mixed-signal block

  • Accurate and efficient simulation of synchronous digital switching noise in system on a chip

    Creator:
    Habal, Husni
    Abstract:
    A new method is presented to compress switching information in large digital circuits. This is combined with an efficient approach of generating the noise signatures of cells in a digital library that results in an accurate and efficient approach for estimating the noise generated in digital circuits. This method provides...
    Resource Type:
    Masters Thesis
    Full Text:
    ................................................................................ 38 A-2. (a) Ideal inverter and (b) inverter with junction capacitance to the substrate and (c

  • Substrate noise coupling analysis in 0.18um silicon germanium (SiGe) and silicon on insulator (SOI) processes

    Creator:
    Pham, Hui En
    Abstract:
    Analysis of substrate noise coupling has been performed for a 0.18¹m lightly doped silicon germanium BiCMOS process. Techniques to minimize noise coupling in the chip and board design are presented, as well as methods for accurate modeling for substrate noise coupling simulations. Measurements from a test chip were taken to...
    Resource Type:
    Masters Thesis
    Full Text:
    2.1 Lumped substrate model. (a) p+ to p+ model. (b) n+ to p+ model. . 4 2.2 Typical cross-section of

  • Energy efficient communication across on-chip wires in digital CMOS

    Creator:
    Postman, Jacob
    Abstract:
    For the past half century, CMOS process scaling has followed Moore's law, approximately doubling transistor density every 18 months. While locally routed wires have generally scaled with transistor size, longer wires have scaled at a slower rate and in some cases have grown larger as chip size and complexity have...
    Resource Type:
    Dissertation
    Full Text:
    versus a baseline NoC and ideal communi- cation. (a) Ideal communication; (b) Baseline NoC; and (c) SWIFT

  • The Architecture of a Reusable Built-In Self-Test for Link Training, IO and Memory Defect Detection and Auto Repair on 14nm Intel SOC

    Creator:
    Querbach, Bruce
    Abstract:
    The complexity of designing and testing today's system on chip (SOC) is increasing due to greater integrated circuit (IC) density and higher IO and memory frequencies. SOCs for the mobile phone and tablet market have the unique challenge of short product development windows, at times less than six months, and...
    Resource Type:
    Dissertation
    Full Text:
    6.4T/S 19 DRAM ORGANIZATION 20 ADJACENT NEIGHBORHOOD OF A MEMORY CELL B 21 DRAM FAULT SIMULATION

  • Power efficient H.264 video decoding in embedded multiprocessor

    Creator:
    Kim, Jihong
    Abstract:
    This thesis presents a novel methodology that enables power efficient video decoding in an embedded system based on MPSoC (Multiprocessor System on Chip). This methodology is a physical combination of parallel processing which reduces power consumption of processors by exploiting thread-level parallelism and Dynamic Voltage Frequency Scaling (DVFS) that allows...
    Resource Type:
    Masters Thesis
    Full Text:
    rounding of the two nearest samples at integer- and half-sample position as follows: ! a = (G + b +1

  • A Multiresolution Analysis of Temporal Logic

    Creator:
    Pelphrey, Richard E.
    Abstract:
    Is it possible to determine whether a signal violates a formula in Signal Temporal Logic (STL), if the monitor only has access to a low-resolution version of the signal? We answer this question affirmatively by demonstrating that temporal logic has a multiresolution structure, which parallels the multiresolution structure of signals....
    Resource Type:
    Masters Thesis
    Full Text:
    . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2 Monitoring x−1 in which a violation is found in plots (b) and (c). . . . . . 27 5.3

  • A DC-DC converter architecture for low-power, high-resistance thermoelectric generators for use in body-powered designs

    Creator:
    Miller, Brian A.
    Abstract:
    This thesis presents a low power DC-DC converter suitable for harvesting energy from high impedance thermoelectric generators (TEGs) for the use in body powered electronics. The chip has been fabricated in a 130nm CMOS technology. To meet the power demands of body powered networks, a novel dual-path architecture capable of...
    Resource Type:
    Masters Thesis
    Full Text:
    architectures. (a) Two converter architecture. (b

  • Foreground signature extraction for a non-linear hyperspectral mixing model

    Creator:
    Hollis, Jarrod
    Abstract:
    Hyperspectral images consist of intensity measurements associated with a large number of EM wavelengths per pixel. When a pixel contains a single material, the measurements of the pixel match the spectral signature of the material. When multiple materials are present in a single pixel, spectral mixing occurs, and signatures of...
    Resource Type:
    Masters Thesis
    Full Text:
    within a single pixel, the measurement is a mixture of several signatures. 2 (a) (b) (c) (d) (e) (f