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Filtering by: Creator Dale, A. C. Remove constraint Creator: Dale, A. C. Academic Affiliation Electrical Engineering and Computer Science Remove constraint Academic Affiliation: Electrical Engineering and Computer Science Language English [eng] Remove constraint Language: English [eng]

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  • Three-Dimensional Network-on-Chip Architectures for Cycle Accurate Full-System Simulator

    Creator:
    Agarwal, Akash
    Abstract:
    High Performance Computing can find ubiquitous applications in the industry. HPC-applications are specifically designed to take advantage of the parallel nature of the computing systems which is often enabled by Multi-core/Many-core architectures. With this advent of Multi-processors in the mainstream systems, inter-core communication has been one of the major challenges...
    Resource Type:
    Presentation and Capstone Project
    Full Text:
    /0beac857ce1af1a531b6538804e71efdef05.pdf. [Accessed Tuesday May 2020]. 7. T. C. Xu, P. Liljeberg and H. Tenhunen, "A study of Through

  • An evaluation of game controllers and tablets as controllers for interactive TV applications

    Creator:
    Cox, Dale J.
    Abstract:
    There is a growing interest in bringing online and streaming content to the television. Gaming platforms such as the PS3, Xbox 360 and Wii are at the center of this digital convergence; platforms for accessing new media services. This presents a number of interface challenges, as controllers designed for gaming...
    Resource Type:
    Masters Thesis
    Full Text:
    Applications by Dale J. Cox A THESIS submitted to Oregon State

  • Accurate and efficient simulation of synchronous digital switching noise in system on a chip

    Creator:
    Habal, Husni
    Abstract:
    A new method is presented to compress switching information in large digital circuits. This is combined with an efficient approach of generating the noise signatures of cells in a digital library that results in an accurate and efficient approach for estimating the noise generated in digital circuits. This method provides...
    Resource Type:
    Masters Thesis
    Full Text:
    ................................................................................ 38 A-2. (a) Ideal inverter and (b) inverter with junction capacitance to the substrate and (c

  • Substrate noise coupling analysis in 0.18um silicon germanium (SiGe) and silicon on insulator (SOI) processes

    Creator:
    Pham, Hui En
    Abstract:
    Analysis of substrate noise coupling has been performed for a 0.18¹m lightly doped silicon germanium BiCMOS process. Techniques to minimize noise coupling in the chip and board design are presented, as well as methods for accurate modeling for substrate noise coupling simulations. Measurements from a test chip were taken to...
    Resource Type:
    Masters Thesis
    Full Text:
    doped p+ channel- 4 P+ x backplane R11 R12 R22 P+ (a) P+N+ R22 R12 R11 backplane x j C

  • Energy efficient communication across on-chip wires in digital CMOS

    Creator:
    Postman, Jacob
    Abstract:
    For the past half century, CMOS process scaling has followed Moore's law, approximately doubling transistor density every 18 months. While locally routed wires have generally scaled with transistor size, longer wires have scaled at a slower rate and in some cases have grown larger as chip size and complexity have...
    Resource Type:
    Dissertation
    Full Text:
    versus a baseline NoC and ideal communi- cation. (a) Ideal communication; (b) Baseline NoC; and (c) SWIFT

  • The Architecture of a Reusable Built-In Self-Test for Link Training, IO and Memory Defect Detection and Auto Repair on 14nm Intel SOC

    Creator:
    Querbach, Bruce
    Abstract:
    The complexity of designing and testing today's system on chip (SOC) is increasing due to greater integrated circuit (IC) density and higher IO and memory frequencies. SOCs for the mobile phone and tablet market have the unique challenge of short product development windows, at times less than six months, and...
    Resource Type:
    Dissertation
    Full Text:
    certain address accesses multiple cells simultaneously c. No address can access a certain cell d

  • Power efficient H.264 video decoding in embedded multiprocessor

    Creator:
    Kim, Jihong
    Abstract:
    This thesis presents a novel methodology that enables power efficient video decoding in an embedded system based on MPSoC (Multiprocessor System on Chip). This methodology is a physical combination of parallel processing which reduces power consumption of processors by exploiting thread-level parallelism and Dynamic Voltage Frequency Scaling (DVFS) that allows...
    Resource Type:
    Masters Thesis
    Full Text:
    availability of left samples (I, J, K, L), upper samples (A, B, C, D) and upper-right samples (E, F, G, H) as

  • IC-Antenna Co-Integration for Efficient and Scalable Millimeter-Wave Antenna Interfaces

    Creator:
    Liu,Yao
    Abstract:
    Millimeter-wave (mm-wave) technology promises high speed, high system capacity and low latency interconnects with reduced cost. Applications like high data-rate wireless links, next generation automotive sensors and security body scanners highly depend on mm-wave technology innovations. As operating frequency moves to higher mm-wave bands, shrinking antenna dimensions enable co-integration of...
    Resource Type:
    Dissertation
    Full Text:
    GHz in the presence of a reflector. c©Copyright by Yao Liu March 8, 2019 All Rights Reserved IC

  • Experimentation of Synchronous and Variable Speed Small Scale Hydropower Systems

    Creator:
    Jackson, Elliott C.
    Abstract:
    Hydropower is the one of the oldest renewable energy technologies and is wrongly thought of today as having little room to grow. The opportunity for new hydropower capacity is immense through both technology advancement and run-of-river new stream reach projects. Despite the age of hydropower, a divide in opinion is...
    Resource Type:
    Masters Thesis
    Full Text:
    , a divide in opinion is forming regarding how we should proceed with generating power from smaller

  • A tunable duty-cycle-controlled switched-R-MOSFET-C CMOS filter for low-voltage and high-linearity applications

    Creator:
    Xiao, Ying
    Abstract:
    A novel switched-R-MOSFET-C input branch is proposed for low-voltage and high-linearity applications. The tunability is achieved by varying the clock duty cycle using an automatic tuning circuit. This tuning method does not involve a change in gate voltage, and is therefore particularly suitable for low-voltage applications. The advantages of the...
    Resource Type:
    Masters Thesis
    Full Text:
    , 2004 . Title: A Tunable Duty-Cycle-Controlled Switched-R-MOSFET-C CMOS Filter for Low-Voltage and