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Filtering by: Creator Katz, Scott B. Remove constraint Creator: Katz, Scott B. Academic Affiliation Electrical Engineering and Computer Science Remove constraint Academic Affiliation: Electrical Engineering and Computer Science Subject Phase-locked loops Remove constraint Subject: Phase-locked loops

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  • Digital phase-locked loops for multi-GHz clock generation

    Creator:
    Kratyuk, Volodymyr
    Abstract:
    A digital implementation of a PLL has several advantages compared to its analog counterpart. These include easy scalability with process shrink, elimination of the noise susceptible analog control for a voltage controlled oscillator (VCO) and the inherent noise immunity of digital circuits. Several recent digital PLL (DPLL) implementations have achieved...
    Resource Type:
    Dissertation
    Full Text:
    ◦. (b) PM=19.6◦. (c) PM=74.4

  • High-speed CMOS dual-modulus presalers for frequency synthesis

    Creator:
    Desikachari, Ranganathan
    Abstract:
    Phase-locked loop (PLL) frequency synthesizers lie at the heart of most radio transceivers. An important objective of the electronics and communications industry is to design high-speed building blocks which dissipate the lowest possible power, and to ac- complish this with the cheapest technology. The dual-modulus prescaler is one of the...
    Resource Type:
    Masters Thesis
    Full Text:
    . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.5 Phase-locked loop (a) block diagram,(b) linear model. . . . . . . . . . . . . . . . . . . 10

  • Design techniques for PVT tolerant phase-locked loops

    Creator:
    Wu, Ting
    Abstract:
    The continued scaling of deep-submicron CMOS technology enables low-voltage high-frequency phase-locked loops (PLLs) to be fully integrated in complex mixed-signal systems. However, fluctuations due to the manufacturing process and variations in environmental conditions, such as supply voltage and temperature, are also significantly increased. As a result, the performance of PLLs...
    Resource Type:
    Dissertation
    Full Text:
    Page 1.1 Continued scaling of CMOS technology. (a) Gate length and local clock frequencies. (b) Supply

  • Design techniques for high-performance digital PLLs and CDRs

    Creator:
    Yin, Wenjing
    Abstract:
    Phase-Locked Loops (PLLs) are essential building blocks in many communication systems. Designing high performance analog PLLs in the presence of technology imposed constraints such as leakage, poor analog transistor behavior, process variability, and low supply voltage is a challenging task. To overcome these drawbacks, digital PLLs (DPLLs) have recently emerged...
    Resource Type:
    Dissertation
    Full Text:
    resolution-tuning range tradeoff. (a) Small LSB. (b) Large LSB. 33 3.5 Block diagram of the simplified

  • Performance enhancement techniques for low power digital phase locked loops

    Creator:
    Elshazly, Amr
    Abstract:
    Desire for low-power, high performance computing has been at core of the symbiotic union between digital circuits and CMOS scaling. While digital circuit performance improves with device scaling, analog circuits have not gained these benefits. As a result, it has become necessary to leverage increased digital circuit performance to mitigate...
    Resource Type:
    Dissertation
    Full Text:
    Brian Fuchs, for the weekly coffee and lunches. Thanks Emily Loo, Scott Griffiths, Anna B., Kaleen

  • Time-based noise-shaping techniques for time-to-digital and analog-to-digital converters

    Creator:
    Young, Brian LeRoy
    Abstract:
    In this dissertation, time-based signal processing techniques and their applications in oversampling and noise-shaping data converters are examined. These techniques demonstrate the ability to shift the burden of high performance analog circuits from the compressed voltage-domain to the augmented time-domain. First, the potential of high order noise-shaping and phase-domain feedback...
    Resource Type:
    Dissertation
    Full Text:
    this manuscript. I would like to thank Ravi Subramanian and Scott Guyton of Berkeley Design Automation

  • Low-power techniques for supply-noise mitigation in phase-locked loops

    Creator:
    Arakali, Abhijith
    Abstract:
    Modern day digital systems employ frequency synthesizers to provide a common clock to the system. They are undergoing large scale integration due to which, mitigation of the effect of noise on power supply has become a major design consideration in clocking circuits. Rapid scaling of CMOS technology mandates the design...
    Resource Type:
    Dissertation
    Full Text:
    Jorden, Zack, Matt, Scott, Jessica, Tiffany, Kaleen, Eunice and Anna for their friendship. I thank Mr