High Performance Computing can find ubiquitous applications in the industry. HPC-applications are specifically designed to take advantage of the parallel nature of the computing systems which is often enabled by Multi-core/Many-core architectures. With this advent of Multi-processors in the mainstream systems, inter-core communication has been one of the major challenges...
Millimeter-wave (mm-wave) technology promises high speed, high system capacity and low latency interconnects with reduced cost. Applications like high data-rate wireless links, next generation automotive sensors and security body scanners highly depend on mm-wave technology innovations. As operating frequency moves to higher mm-wave bands, shrinking antenna dimensions enable co-integration of...
A new method is presented to compress switching information in large digital circuits. This is combined with an efficient approach of generating the noise signatures of cells in a digital library that results in an accurate and efficient approach for estimating the noise generated in digital circuits. This method provides...
Analysis of substrate noise coupling has been performed for a 0.18¹m lightly doped silicon germanium BiCMOS process. Techniques to minimize noise coupling in the chip and board design are presented, as well as methods for accurate modeling for substrate noise coupling simulations. Measurements from a test chip were taken to...
For the past half century, CMOS process scaling has followed Moore's law, approximately doubling transistor density every 18 months. While locally routed wires have generally scaled with transistor size, longer wires have scaled at a slower rate and in some cases have grown larger as chip size and complexity have...
The increasing demand for higher data-rates is challenging to satisfy with spectrum-deficient indoor WiFi networks. A novel hybrid WiFi Free-Space Optical (WIFO) system has been proposed to enhance the wireless capacity of indoor WiFi networks. In this thesis, an integrated optical wireless receiver is designed and integrated in 65-nm CMOS...
The complexity of designing and testing today's system on chip (SOC) is increasing due to greater integrated circuit (IC) density and higher IO and memory frequencies. SOCs for the mobile phone and tablet market have the unique challenge of short product development windows, at times less than six months, and...
This thesis presents a novel methodology that enables power efficient video decoding
in an embedded system based on MPSoC (Multiprocessor System on Chip). This
methodology is a physical combination of parallel processing which reduces power
consumption of processors by exploiting thread-level parallelism and Dynamic
Voltage Frequency Scaling (DVFS) that allows...
Frequency synthesizers are critical components of all communication systems. This thesis considers the issue of undesirable frequency spurs of a relatively recent type of frequency synthesis architecture called digital-to-time conversion (DTC). The DTC-based frequency synthesis architecture has important performance benefits over older frequency synthesizers, such as fast frequency switching, large...
Ultra-high-speed (>10GS/s), medium-resolution (5~6bit), low-power (<50mW) analog-to-digital converter can find it application in the areas of digital oscilloscopes and next-generation serial link receivers. There are several challenges to enable a successful design, however. First, the time-interleaved architecture is required in order to achieve over 10GS/s sampling rate, with the trade-off...