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Filtering by: Creator Hirst, A. G. Remove constraint Creator: Hirst, A. G. Academic Affiliation Electrical Engineering and Computer Science Remove constraint Academic Affiliation: Electrical Engineering and Computer Science

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  • Three-Dimensional Network-on-Chip Architectures for Cycle Accurate Full-System Simulator

    Creator:
    Agarwal, Akash
    Abstract:
    High Performance Computing can find ubiquitous applications in the industry. HPC-applications are specifically designed to take advantage of the parallel nature of the computing systems which is often enabled by Multi-core/Many-core architectures. With this advent of Multi-processors in the mainstream systems, inter-core communication has been one of the major challenges...
    Resource Type:
    Presentation and Capstone Project
    Full Text:
    . Lizhong Chen Assistant Professor EECS, Oregon State University • Moore: Number of transistors in a

  • Accurate and efficient simulation of synchronous digital switching noise in system on a chip

    Creator:
    Habal, Husni
    Abstract:
    A new method is presented to compress switching information in large digital circuits. This is combined with an efficient approach of generating the noise signatures of cells in a digital library that results in an accurate and efficient approach for estimating the noise generated in digital circuits. This method provides...
    Resource Type:
    Masters Thesis
    Full Text:
    Efficient Simulation of Synchronous Digital Switching Noise in Systems on a Chip Abstract approved

  • Substrate noise coupling analysis in 0.18um silicon germanium (SiGe) and silicon on insulator (SOI) processes

    Creator:
    Pham, Hui En
    Abstract:
    Analysis of substrate noise coupling has been performed for a 0.18¹m lightly doped silicon germanium BiCMOS process. Techniques to minimize noise coupling in the chip and board design are presented, as well as methods for accurate modeling for substrate noise coupling simulations. Measurements from a test chip were taken to...
    Resource Type:
    Masters Thesis
    Full Text:
    case with a moat, S is the case with the bulks and sources separated, and G is the case with the DPR

  • Energy efficient communication across on-chip wires in digital CMOS

    Creator:
    Postman, Jacob
    Abstract:
    For the past half century, CMOS process scaling has followed Moore's law, approximately doubling transistor density every 18 months. While locally routed wires have generally scaled with transistor size, longer wires have scaled at a slower rate and in some cases have grown larger as chip size and complexity have...
    Resource Type:
    Dissertation
    Full Text:
    , longer wires have scaled at a slower rate and in some cases have grown larger as chip size and

  • Protein secondary structure prediction using conditional random fields and profiles

    Creator:
    Shen, Rongkun
    Abstract:
    Protein secondary structure prediction plays a pivotal role in predicting protein folding in three-dimensions. Its task is to assign each residue one of the three secondary structure classes helix, strand, or random coil. This is an instance of the problem of sequential supervised learning in machine learning. This thesis describes...
    Resource Type:
    Masters Thesis
    Full Text:
    et al (2001) proposed: ( ) ( )1 1 , ( , ) , , ( , , ) i a a i a i i b b i i b y X g y X y y

  • A methodology to reduce the strain on hydro turbines using advanced life extending control of multiple energy storage systems

    Creator:
    Brosig, Sean G.
    Abstract:
    Over the last 20 years, there has been rapid growth in the amount of installed wind power in the Pacific Northwest, specifically in the Columbia River Gorge. The variable and non-dispatchable nature of this resource requires that it be balanced in some form by other sources on the grid. In...
    Resource Type:
    Masters Thesis
    Full Text:
    . ©Copyright by Sean G. Brosig June 13, 2013 All Rights Reserved A Methodology to Reduce the Strain

  • The Architecture of a Reusable Built-In Self-Test for Link Training, IO and Memory Defect Detection and Auto Repair on 14nm Intel SOC

    Creator:
    Querbach, Bruce
    Abstract:
    The complexity of designing and testing today's system on chip (SOC) is increasing due to greater integrated circuit (IC) density and higher IO and memory frequencies. SOCs for the mobile phone and tablet market have the unique challenge of short product development windows, at times less than six months, and...
    Resource Type:
    Dissertation
    Full Text:
    , D. G. Ellis, A. Khan, M. J. Tripp, E. S. Gayles, and E. Gollapudi, Automatic self test of an

  • Power efficient H.264 video decoding in embedded multiprocessor

    Creator:
    Kim, Jihong
    Abstract:
    This thesis presents a novel methodology that enables power efficient video decoding in an embedded system based on MPSoC (Multiprocessor System on Chip). This methodology is a physical combination of parallel processing which reduces power consumption of processors by exploiting thread-level parallelism and Dynamic Voltage Frequency Scaling (DVFS) that allows...
    Resource Type:
    Masters Thesis
    Full Text:
    horizontal integer samples E, F, G, H, I and J, and h is calculated from the six vertical integer samples A

  • IC-Antenna Co-Integration for Efficient and Scalable Millimeter-Wave Antenna Interfaces

    Creator:
    Liu,Yao
    Abstract:
    Millimeter-wave (mm-wave) technology promises high speed, high system capacity and low latency interconnects with reduced cost. Applications like high data-rate wireless links, next generation automotive sensors and security body scanners highly depend on mm-wave technology innovations. As operating frequency moves to higher mm-wave bands, shrinking antenna dimensions enable co-integration of...
    Resource Type:
    Dissertation
    Full Text:
    commu- nication and radar link budgets. This dissertation presents a wafer-scale compatible IC-antenna

  • A Benchmarking Study of Unsupervised Anomaly Detection Algorithms

    Creator:
    Emmott, Andrew F.
    Abstract:
    It is common practice in the unsupervised anomaly detection literature to create experimental benchmarks by sampling from existing supervised learning datasets. We seek to improve this practice by identifying four dimensions important to real-world anomaly detection applications --- point difficulty, clusteredness of anomalies, relevance of features, and relative frequency of...
    Resource Type:
    Masters Thesis
    Full Text:
    degree of Master of Science in Computer Science presented on June 18, 2020. Title: A Benchmarking Study