Search Constraints

Start Over
Filtering by: Subject Integrated passive components -- Design and construction Remove constraint Subject: Integrated passive components -- Design and construction Academic Affiliation Electrical Engineering and Computer Science Remove constraint Academic Affiliation: Electrical Engineering and Computer Science

Search Results

  • Design of compact folded-line RF power dividers

    Creator:
    Lim, Chi-young
    Abstract:
    Embedded passives in multi-layer media have gained importance for offering an attractive solution to the implementation of off-chip passive components in RF and mixed signal circuits, especially for wireless applications. Among the passive devices, power dividers and combiners are extensively used for a host of applications including balanced mixers, phase...
    Resource Type:
    Masters Thesis

  • Enabling metal-fill-aware design of integrated circuits

    Creator:
    Shilimkar, Vikas S.
    Abstract:
    In advanced integrated circuit (IC) processes, the metal fill inserted to meet foundry imposed density requirements degrades the performance of interconnects and passive components which ultimately affects the overall circuit performance. Accounting for this degradation through electromagnetic and equivalent circuit modeling is becoming a critical aspect of IC design. However,...
    Resource Type:
    Dissertation
    Full Text:
    availability of computationally efficient models for component design. As the accurate estimation of passive

  • Low power scheduling schemes that consider latency and resource constraints at multiple voltages

    Creator:
    Huang, Shyh-Sen
    Abstract:
    Power reduction can be achieved at many different levels, such as architecture, algorithm, logic, and transistor levels in circuit design. This thesis focuses on low power scheduling at the algorithm level. We present a latency-constrained scheduling and a latency and resource constrained scheduling, which minimize power consumption for the resources...
    Resource Type:
    Masters Thesis
    Full Text:
    FIGURES Figure Page 1. Design Flow and the Levels of Abstraction

  • Design techniques for clocking high performance signaling systems

    Creator:
    Hanumolu, Pavan Kumar
    Abstract:
    Scaling of CMOS technology has progressed relentlessly for the past several decades. In order for this unprecedented scaling to benefit the performance of large digital systems, the communication bandwidth between integrated circuits (ICs) must scale accordingly. However, interconnect technology does not scale as aggressively, making communication between chips the major...
    Resource Type:
    Dissertation
    Full Text:
    being 3000 miles away and generously shared his vast knowledge on links design. Gu masterfully

  • Analysis and modeling of single-ended and differential spiral inductors in silicon-based RFICs

    Creator:
    Watson, Adam C.
    Abstract:
    A new comprehensive wide-band compact modeling methodology for single-ended spiral inductors and differential spiral inductors is presented. The new modeling methodology creates an equivalent circuit model consisting of frequency-independent circuit elements for use in circuit simulators. A fast automated extraction procedure is developed for determining the circuit element values from...
    Resource Type:
    Masters Thesis
    Full Text:
    creation of "System on Chip" (SoC) and "Application Specific Integrated Circuits" (ASIC). The SoC design

  • Metal fill considerations for on-chip interconnects and spiral inductors

    Creator:
    Shilimkar, Vikas S.
    Abstract:
    Variability in circuit performance due to process defects is a major concern in integrated circuit (IC) fabrication. Advanced IC manufacturing processes employ Chemical-Mechanical Polishing (CMP) for planarization of oxide and metal layers. CMP defects result in variations in the oxide and metal topographical profile. To reduce these topographical variations, electrically...
    Resource Type:
    Masters Thesis
    Full Text:
    advancements in integrated circuits (IC) technologies, design, and fabri- cation have significantly improved

  • Low power design techniques for high speed pipelined ADCs

    Creator:
    Lingam, Naga Sasidhar
    Abstract:
    Real world is analog but the processing of signals can best be done in digital domain. So the need for Analog to Digital Converters(ADCs) is ever rising as more and more applications set in. With the advent of mobile technology, power in electronic equipment is being driven down to get...
    Resource Type:
    Dissertation
    Full Text:
    Philosophy in Electrical and Computer Engineering presented on January 12, 2009. Title: Low Power Design

  • Low voltage techniques for pipelined analog-to-digital converters

    Creator:
    Carnes, Joshua Kenneth
    Abstract:
    To realize pipelined ADCs in deep-submicron processes, low voltage techniques must be developed to work around problems created by limited supply voltages such as the floating switch dead zone, reduced SNR, and reduced OpAmp performance. This thesis analyzes standard and low voltage design issues for pipelined ADCs and proposes a...
    Resource Type:
    Masters Thesis
    Full Text:
    and low voltage design issues for pipelined ADCs and proposes a fully-differential implementation of

  • Characterization of a digital phase locked loop and a stochastic time to digital converter

    Creator:
    Geissenhainer, Erik D.
    Abstract:
    A digital phase locked loop (DPLL) and a statistical time-to-digital converter (STDC) were previously fabricated in a 0.35µm, 3.3V SOI CMOS process. This work summarizes these designs and characterizes the measured performance. Simulations supplement the measurements where applicable. The DPLL was found to reach a locked state under a limited...
    Resource Type:
    Masters Thesis
    Full Text:
    , there is a desire to combine the PLL circuitry and other system components onto a single integrated

  • Analysis and modeling of multi-mode effects in coplanar waveguide bends

    Creator:
    Senguttuvan, Rajarajan
    Abstract:
    A novel method for modeling bends in coplanar waveguides (CPWs) is described. The CPW can be viewed as a pair of parallel coupled quasi-slot lines. Bends in the CPW are modeled as a non-uniform coupled line system in terms of their even- and odd- mode characteristics. This modeling approach is...
    Resource Type:
    Masters Thesis
    Full Text:
    flexibility in the design of CPWs for RF circuits and integration with other components on the circuit board