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Filtering by: Creator Morey, A. E. Remove constraint Creator: Morey, A. E. Academic Affiliation Electrical Engineering and Computer Science Remove constraint Academic Affiliation: Electrical Engineering and Computer Science

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  • Three-Dimensional Network-on-Chip Architectures for Cycle Accurate Full-System Simulator

    Creator:
    Agarwal, Akash
    Abstract:
    High Performance Computing can find ubiquitous applications in the industry. HPC-applications are specifically designed to take advantage of the parallel nature of the computing systems which is often enabled by Multi-core/Many-core architectures. With this advent of Multi-processors in the mainstream systems, inter-core communication has been one of the major challenges...
    Resource Type:
    Presentation and Capstone Project
    Full Text:
    . Lizhong Chen Assistant Professor EECS, Oregon State University • Moore: Number of transistors in a

  • Accurate and efficient simulation of synchronous digital switching noise in system on a chip

    Creator:
    Habal, Husni
    Abstract:
    A new method is presented to compress switching information in large digital circuits. This is combined with an efficient approach of generating the noise signatures of cells in a digital library that results in an accurate and efficient approach for estimating the noise generated in digital circuits. This method provides...
    Resource Type:
    Masters Thesis
    Full Text:
    . 8 a) E 4 0) (0 a) 2 Cl) 0 z 0 10 8 a) E 4- 0) (0 2 U) z Figure 5.2 Spice Simulation

  • Substrate noise coupling analysis in 0.18um silicon germanium (SiGe) and silicon on insulator (SOI) processes

    Creator:
    Pham, Hui En
    Abstract:
    Analysis of substrate noise coupling has been performed for a 0.18¹m lightly doped silicon germanium BiCMOS process. Techniques to minimize noise coupling in the chip and board design are presented, as well as methods for accurate modeling for substrate noise coupling simulations. Measurements from a test chip were taken to...
    Resource Type:
    Masters Thesis
    Full Text:
    . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 E-21 Measured (top) and simulated (bottom) transient output of amp1 without a moat, with step1

  • Energy efficient communication across on-chip wires in digital CMOS

    Creator:
    Postman, Jacob
    Abstract:
    For the past half century, CMOS process scaling has followed Moore's law, approximately doubling transistor density every 18 months. While locally routed wires have generally scaled with transistor size, longer wires have scaled at a slower rate and in some cases have grown larger as chip size and complexity have...
    Resource Type:
    Dissertation
    Full Text:
    , longer wires have scaled at a slower rate and in some cases have grown larger as chip size and

  • Design and implementation of configuration modules in a programmable hardware-assisted cache emulator (PHA$E)

    Creator:
    Chalainanont, Nirut
    Abstract:
    Memory hierarchy design is becoming more important as the speed gap be- tween processor and memory continues to grow. Investigations of memory perfor- mance have typically been conducted using trace-driven emulation, which could take tremendous resources (e.g. long emulation time, large storage requirements for traces, and high overall cost). Recent...
    Resource Type:
    Masters Thesis
    Full Text:
    work with the Programmable Hardware Assisted Cache Emulator (PHA$E), a system for emulating cache in

  • The Architecture of a Reusable Built-In Self-Test for Link Training, IO and Memory Defect Detection and Auto Repair on 14nm Intel SOC

    Creator:
    Querbach, Bruce
    Abstract:
    The complexity of designing and testing today's system on chip (SOC) is increasing due to greater integrated circuit (IC) density and higher IO and memory frequencies. SOCs for the mobile phone and tablet market have the unique challenge of short product development windows, at times less than six months, and...
    Resource Type:
    Dissertation
    Full Text:
    . O’Mahony, M. Mansuri, K. Canagasaby, J. Kennedy, E. Yeung, and R. Mooney, “A 20Gb/s Forwarded Clock

  • Power efficient H.264 video decoding in embedded multiprocessor

    Creator:
    Kim, Jihong
    Abstract:
    This thesis presents a novel methodology that enables power efficient video decoding in an embedded system based on MPSoC (Multiprocessor System on Chip). This methodology is a physical combination of parallel processing which reduces power consumption of processors by exploiting thread-level parallelism and Dynamic Voltage Frequency Scaling (DVFS) that allows...
    Resource Type:
    Masters Thesis
    Full Text:
    horizontal integer samples E, F, G, H, I and J, and h is calculated from the six vertical integer samples A

  • IC-Antenna Co-Integration for Efficient and Scalable Millimeter-Wave Antenna Interfaces

    Creator:
    Liu,Yao
    Abstract:
    Millimeter-wave (mm-wave) technology promises high speed, high system capacity and low latency interconnects with reduced cost. Applications like high data-rate wireless links, next generation automotive sensors and security body scanners highly depend on mm-wave technology innovations. As operating frequency moves to higher mm-wave bands, shrinking antenna dimensions enable co-integration of...
    Resource Type:
    Dissertation
    Full Text:
    commu- nication and radar link budgets. This dissertation presents a wafer-scale compatible IC-antenna

  • Studies to inform a visual language for authoring interactive exercise prescriptions

    Creator:
    Dodge, Jonathan E.
    Abstract:
    Communicating dynamic motion content, such as exercise, with a static medium, such as paper, is difficult. The technology exists for presenting 3D animated exercise content to patients; however, the tools for allowing exercise domain experts to effectively author the content do not exist. We conducted two formative studies with exercise...
    Resource Type:
    Masters Thesis
    Full Text:
    organization. 24 Table 4.2: Results for Question 1 - Create a Prescription A B C D E F G H I J Frequency

  • Computing Substation Fragility as a Function of Seismic Component Failure

    Creator:
    Stark, William D.
    Abstract:
    The electrical grid of the Western Interconnection is vulnerable to earthquake damage, especially large-magnitude megathrust events, due to the unique seismic profile of the region. However, the size of the Western Interconnection makes it difficult to model seismic failure in electrical substations to the level of detail necessary to improve...
    Resource Type:
    Masters Thesis
    Full Text:
    ro b a b ili ty o f F a ilu re R(s)=0.89365 R(m)=0.99369 R(e)=0.98148 R(c)=0.71151