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  • Three-Dimensional Network-on-Chip Architectures for Cycle Accurate Full-System Simulator

    Creator:
    Agarwal, Akash
    Abstract:
    High Performance Computing can find ubiquitous applications in the industry. HPC-applications are specifically designed to take advantage of the parallel nature of the computing systems which is often enabled by Multi-core/Many-core architectures. With this advent of Multi-processors in the mainstream systems, inter-core communication has been one of the major challenges...
    Resource Type:
    Presentation and Capstone Project
    Full Text:
    . Lizhong Chen Assistant Professor EECS, Oregon State University • Moore: Number of transistors in a

  • Energy efficient communication across on-chip wires in digital CMOS

    Creator:
    Postman, Jacob
    Abstract:
    For the past half century, CMOS process scaling has followed Moore's law, approximately doubling transistor density every 18 months. While locally routed wires have generally scaled with transistor size, longer wires have scaled at a slower rate and in some cases have grown larger as chip size and complexity have...
    Resource Type:
    Dissertation
    Full Text:
    Energy = Wire Energy (a) R N R R R N 3-cycle 3-cycle 3-cycle 3-cycle Baseline NoC Delay >= 17

  • The Architecture of a Reusable Built-In Self-Test for Link Training, IO and Memory Defect Detection and Auto Repair on 14nm Intel SOC

    Creator:
    Querbach, Bruce
    Abstract:
    The complexity of designing and testing today's system on chip (SOC) is increasing due to greater integrated circuit (IC) density and higher IO and memory frequencies. SOCs for the mobile phone and tablet market have the unique challenge of short product development windows, at times less than six months, and...
    Resource Type:
    Dissertation
    Full Text:
    . O’Mahony, M. Mansuri, K. Canagasaby, J. Kennedy, E. Yeung, and R. Mooney, “A 20Gb/s Forwarded Clock

  • Substrate noise coupling analysis in 0.18um silicon germanium (SiGe) and silicon on insulator (SOI) processes

    Creator:
    Pham, Hui En
    Abstract:
    Analysis of substrate noise coupling has been performed for a 0.18¹m lightly doped silicon germanium BiCMOS process. Techniques to minimize noise coupling in the chip and board design are presented, as well as methods for accurate modeling for substrate noise coupling simulations. Measurements from a test chip were taken to...
    Resource Type:
    Masters Thesis
    Full Text:
    approved: Terri Fiez Karti Mayaram Analysis of substrate noise coupling has been performed for a 0.18µm

  • Accurate and efficient simulation of synchronous digital switching noise in system on a chip

    Creator:
    Habal, Husni
    Abstract:
    A new method is presented to compress switching information in large digital circuits. This is combined with an efficient approach of generating the noise signatures of cells in a digital library that results in an accurate and efficient approach for estimating the noise generated in digital circuits. This method provides...
    Resource Type:
    Masters Thesis
    Full Text:
    Efficient Simulation of Synchronous Digital Switching Noise in Systems on a Chip Abstract approved

  • A remotely operated, autonomous wave energy converter system

    Creator:
    Lewis, Timothy M.
    Abstract:
    The potential for electric energy generation from ocean waves is substantial and much research is being conducted on the conversion process as a renewable, grid-connected, power source. Some of the same attributes that make wave energy harvesting attractive as a grid-connected source also make it attractive as a remote, or...
    Resource Type:
    Dissertation
    Full Text:
    Electrical and Computer Engineering presented on March 18, 2014. Title: A Remotely Operated

  • Mental Models of Mere Mortals with Explanations of Reinforcement Learning

    Creator:
    Anderson, Andrew A.
    Abstract:
    How should reinforcement learning (RL) agents explain themselves to humans not trained in AI? To gain insights into this question, we conducted a 124 participant, four-treatment experiment to compare participants’ mental models of an RL agent in the context of a simple Real-Time Strategy (RTS) game. The four treatments isolated...
    Resource Type:
    Masters Thesis
    Full Text:
    vector ~R(s, a), which gives the reward for each type. The total scalar reward is the sum across types

  • A tunable duty-cycle-controlled switched-R-MOSFET-C CMOS filter for low-voltage and high-linearity applications

    Creator:
    Xiao, Ying
    Abstract:
    A novel switched-R-MOSFET-C input branch is proposed for low-voltage and high-linearity applications. The tunability is achieved by varying the clock duty cycle using an automatic tuning circuit. This tuning method does not involve a change in gate voltage, and is therefore particularly suitable for low-voltage applications. The advantages of the...
    Resource Type:
    Masters Thesis
    Full Text:
    , 2004 . Title: A Tunable Duty-Cycle-Controlled Switched-R-MOSFET-C CMOS Filter for Low-Voltage and

  • IC-Antenna Co-Integration for Efficient and Scalable Millimeter-Wave Antenna Interfaces

    Creator:
    Liu,Yao
    Abstract:
    Millimeter-wave (mm-wave) technology promises high speed, high system capacity and low latency interconnects with reduced cost. Applications like high data-rate wireless links, next generation automotive sensors and security body scanners highly depend on mm-wave technology innovations. As operating frequency moves to higher mm-wave bands, shrinking antenna dimensions enable co-integration of...
    Resource Type:
    Dissertation
    Full Text:
    . A good candidate for the antenna substrate should have a small value of dielectric constant �r

  • Power efficient H.264 video decoding in embedded multiprocessor

    Creator:
    Kim, Jihong
    Abstract:
    This thesis presents a novel methodology that enables power efficient video decoding in an embedded system based on MPSoC (Multiprocessor System on Chip). This methodology is a physical combination of parallel processing which reduces power consumption of processors by exploiting thread-level parallelism and Dynamic Voltage Frequency Scaling (DVFS) that allows...
    Resource Type:
    Masters Thesis
    Full Text:
    : ______________________________________________________ Ben Lee This thesis presents a novel methodology that enables power efficient video