Index Catalog // ScholarsArchive@OSU

Ultra-low energy digital logic controller design for wireless sensor networks

Creator:: Meliza, Stephen W.
Abstract:: Low energy design techniques for digital circuits are examined to determine their suitability for use in a digital logic controller for wireless sensor network nodes. Transistor level simulations are used to evaluate the techniques and those demonstrating an energy reduction are used to implement a digital logic controller. The digital...
Resource Type:: Masters Thesis

TekBots : a platform for learning to revitalize undergraduate engineering education

Creator:: Heer, Donald
Abstract:: In 2000 the Electrical and Computer Engineering department at Oregon State University began a new and innovative program named TekBots[superscript TM]. This program was created to solve the problems of students in existing undergraduate engineering education not having sufficient skill when graduating in six program educational objectives; Depth, Breadth, Professionalism,...
Resource Type:: Masters Thesis

Simulation, measurement, and suppression of digital noise in mixed-signal integrated circuits

Creator:: Owens, Brian E.
Abstract:: Strategies for simulation and measurement of substrate noise have been analyzed using various digital and analog circuits fabricated in the TSMC 0.35um heavily doped CMOS process. The measurements validate a substrate noise coupling macromodel that has been used to obtain the simulation results. The simulations and measurements also substantiate the...
Resource Type:: Masters Thesis

Simulation and modeling of substrate noise generation from synchronous and asynchronous digital logic circuits

Creator:: Hanken, Christopher
Abstract:: Efficient methods for simulating the substrate noise generated by complex synchronous and asynchronous digital logic circuits are presented. By simulating digital logic at the gate level, and precharacterizing the gates, the substrate noise generation can be predicted and used in a transistor level simulation of the sensitive analog blocks. This...
Resource Type:: Masters Thesis

Silencer! : a tool for substrate noise coupling analysis

Creator:: Birrer, Patrick
Abstract:: This thesis presents Silencer!, a fully automated, schematic-driven tool for substrate noise coupling simulation and analysis. It has been integrated in the CADENCE DFII environment and seamlessly enables substrate coupling analysis in a standard mixed-signal design flow. Silencer! aids IC designers in the analysis of substrate noise coupling at different...
Resource Type:: Masters Thesis

Predictive methodologies for substrate parasitic extraction and modeling in heavily doped CMOS substrates

Creator:: Sharma, Ajit
Abstract:: This thesis presents an automated methodology to calibrate the substrate profile for accurate prediction of substrate parasitics using Green's function based extractors. The technique requires fabrication of only a few test structures and results in an accurate three layered approximation of a heavily doped epitaxial silicon substrate. The obtained substrate...
Resource Type:: Masters Thesis

Prediction of phase noise and jitter in ring oscillators

Creator:: Barton, Nathen
Abstract:: This thesis presents distinctly different methods of accurately predicting phase noise and absolute jitter in ring oscillators. The phase noise prediction methods are the commercially available SpectreRF and isf_tool, a simulator developed in this work from the Hajimiri and Lee theory of phase noise. Absolute jitter due to deterministic supply...
Resource Type:: Masters Thesis

Extending the TekBots [superscript TM] Platform for Learning [superscript TM] to upper division ECE courses

Creator:: Smit, Adriaan
Abstract:: In April of 1997 it was pointed out at an NSF Engineering Education Innovators conference that “… education appears to ignore the need for connections and for integration – which should be at the core of an engineering education.” In order to solve this problem a group named ‘TekBotsTM’ was...
Resource Type:: Masters Thesis

Design of sample and holds using CCDs in a standard CMOS process

Creator:: Ghatak, Kalyan Brata
Abstract:: The parasitic components of MOS switches at high speeds affect the linearity and resolution of CMOS sample and hold circuits. CCD-based circuit design can offer good performance at high speeds. This thesis presents the design of sample and hold circuits using charge-coupled device structures in a standard CMOS process. Three...
Resource Type:: Masters Thesis

Design of current-mode track and hold circuits

Creator:: Chennam, Madhusudhan
Abstract:: A differential current-mode track-and-hold (T/H) amplifier is used to sample an analog input signal. A new closed-loop current-mode architecture has been developed that overcomes the stability problems associated with closed-loop architectures. The T/H circuit has been fabricated in a 0.35-μm quad-metal, double-poly CMOS process. The measured total harmonic distortion (THD)...
Resource Type:: Masters Thesis

Design of a variable gain, high linearity, low power baseband filter for WLAN transmitters

Creator:: Ranganathan, Sachin
Abstract:: A variable gain, high linearity, low power baseband filter for WLAN applications is implemented in a 1.5 V 3 V 0.15 μm CMOS process. This fourth-order low-pass filter, which is introduced in the transmit channel as a reconstruction filter between the D/A converter and the mixer, has a measured cut-off...
Resource Type:: Masters Thesis

Design methodology for low-jitter phase-locked loops

Creator:: Bhagavatheeswaran, Shanthi, S.
Abstract:: This thesis presents a systematic top-down methodology for simulating a phase-locked loop using a macro model in Verilog-A. The macromodel has been used to evaluate the jitter due to supply noise, thermal noise, and ground bounce. The noise simulation with the behavioral model is roughly 310 times faster (best case)...
Resource Type:: Masters Thesis

Comparison and impact of substrate noise due to clocked and clockless circuitry

Creator:: Le, Jim K.
Abstract:: Delay insensitive asynchronous circuitry provides significant advantages with respect to substrate noise due to localized switching. The differences between the substrate noise from NULL Convention Logic (NCL) and traditional Clocked Boolean Logic (CBL) are described and analyzed based on measured results. A test chip fabricated in the TSMC 0.25 um...
Resource Type:: Masters Thesis

Analysis and modeling of substrate noise coupling for NMOS transistors in heavily doped substrates

Creator:: Hsu, Shu-ching
Abstract:: This thesis examines substrate noise coupling for NMOS transistors in heavily doped substrates. The study begins with the analysis of an NMOS transistor switching noise in a digital inverter at the device level. A resistive substrate network for the NMOS transistor is proposed and verified. Coupling between N+- P+ contacts...
Resource Type:: Masters Thesis

An ultra low power frequency reference for timekeeping applications

Creator:: Oporta, Hector Ivan
Abstract:: An ultra low power crystal oscillator that provides a frequency reference for battery powered timekeeping applications is presented. An amplitude control circuit is employed to ensure that minimum current is consumed. A subthreshold voltage regulator provides a supply voltage for the oscillator with minimum current consumption. The oscillator and regulator...
Resource Type:: Masters Thesis

An enhanced swing differential Colpitts CMOS VCO for low-voltage operation

Creator:: Farahbakhshian, Farhad
Abstract:: An enhanced swing differential Colpitts VCO (ESDC-VCO) dramatically improves the swing of a Colpitts VCO by allowing the signal to swing below ground and above the supply voltage. Fabricated in a 1P8M 0.13 um CMOS process, the ESDC-VCO operates at 4.9GHz with a 0.475-V supply and consumes 2.7mW. The measured...
Resource Type:: Masters Thesis

An efficient and accurate method of estimating substrate noise coupling in heavily doped substrates

Creator:: Arunachalam, Sasi Kumar S.
Abstract:: This thesis presents a Z-parameter based model to predict the substratenoise coupling between two contacts in a heavily doped substrate for frequenciesless than 2 GHz. The empirical model is scalable with contact size and spacingsbetween the contacts and model parameters can be readily extracted from simu-lated or measured data. The...
Resource Type:: Masters Thesis

A substrate noise coupling model for lightly doped CMOS processes

Creator:: Sadate, Aline C.
Abstract:: This thesis presents a design-oriented model for lightly doped CMOS substrates. The model predicts the substrate noise coupling between noisy digital and sensitive analog blocks in the early stages of the design. The model scales with the size and separation of these blocks and it is validated with device simulations...
Resource Type:: Masters Thesis

A nano-power wake-up circuit for RF energy harvesting wireless sensor networks

Creator:: Lindsley, Christopher J.
Abstract:: A fully integrated CMOS latched comparator is presented for use as a wake-up circuit that is attached to an RF energy harvester in a battery free wireless sensor network. The system consumes less than 36nA static current at 20°C and dissipates 2pJ of energy per conversion. The comparator comprises of...
Resource Type:: Masters Thesis

A methodology for efficient substrate noise estimation from large scale digital circuits in mixed signal SoC's

Creator:: Held, Martin A.
Abstract:: A methodology for rapid estimation of substrate noise generated by digital circuitry in mixed-signal circuits is presented. This methodology is incorporated into the Silencer! framework, and also provides for future improvements including pre-layout noise estimation. Measurements of a test chip fabricated in the TSMC o.25[mu]m heavily doped logic process validate...
Resource Type:: Masters Thesis

ScholarsArchive@OSU

Ultra-low energy digital logic controller design for wireless sensor networks

TekBots : a platform for learning to revitalize undergraduate engineering education

Simulation, measurement, and suppression of digital noise in mixed-signal integrated circuits

Simulation and modeling of substrate noise generation from synchronous and asynchronous digital logic circuits

Silencer! : a tool for substrate noise coupling analysis

Predictive methodologies for substrate parasitic extraction and modeling in heavily doped CMOS substrates

Prediction of phase noise and jitter in ring oscillators

Extending the TekBots [superscript TM] Platform for Learning [superscript TM] to upper division ECE courses

Design of sample and holds using CCDs in a standard CMOS process

Design of current-mode track and hold circuits

Design of a variable gain, high linearity, low power baseband filter for WLAN transmitters

Design methodology for low-jitter phase-locked loops

Comparison and impact of substrate noise due to clocked and clockless circuitry

Analysis and modeling of substrate noise coupling for NMOS transistors in heavily doped substrates

An ultra low power frequency reference for timekeeping applications

An enhanced swing differential Colpitts CMOS VCO for low-voltage operation

An efficient and accurate method of estimating substrate noise coupling in heavily doped substrates

A substrate noise coupling model for lightly doped CMOS processes

A nano-power wake-up circuit for RF energy harvesting wireless sensor networks

A methodology for efficient substrate noise estimation from large scale digital circuits in mixed signal SoC's

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