Index Catalog // ScholarsArchive@OSU

Simulation, measurement, and suppression of digital noise in mixed-signal integrated circuits

Creator:: Owens, Brian E.
Abstract:: Strategies for simulation and measurement of substrate noise have been analyzed using various digital and analog circuits fabricated in the TSMC 0.35um heavily doped CMOS process. The measurements validate a substrate noise coupling macromodel that has been used to obtain the simulation results. The simulations and measurements also substantiate the...
Resource Type:: Masters Thesis

A DC-DC converter architecture for low-power, high-resistance thermoelectric generators for use in body-powered designs

Creator:: Miller, Brian A.
Abstract:: This thesis presents a low power DC-DC converter suitable for harvesting energy from high impedance thermoelectric generators (TEGs) for the use in body powered electronics. The chip has been fabricated in a 130nm CMOS technology. To meet the power demands of body powered networks, a novel dual-path architecture capable of...
Resource Type:: Masters Thesis
Full Text:: Thermoelectric Generators for use in Body-Powered Designs AN ABSTRACT OF THE THESIS OF Brian

Noise and Blocker Cancellation Techniques for Power and Area Efficient Wireless Receivers

Creator:: Pourbagheri, Saeed
Abstract:: The design of mobile wireless devices has always focused on reducing power, area, and cost. This dissertation proposes two techniques that are leveraged to save power and area and therefore cost. The first techniques reduces the noise in the receiver and results in a relaxed power requirement. The second technique...
Resource Type:: Dissertation
Full Text:: thank Dr. Huaping Liu, Dr. Arun Natarajan and Dr. Brian Paul for serving in my committee. My

A methodology for efficient substrate noise estimation from large scale digital circuits in mixed signal SoC's

Creator:: Held, Martin A.
Abstract:: A methodology for rapid estimation of substrate noise generated by digital circuitry in mixed-signal circuits is presented. This methodology is incorporated into the Silencer! framework, and also provides for future improvements including pre-layout noise estimation. Measurements of a test chip fabricated in the TSMC o.25[mu]m heavily doped logic process validate...
Resource Type:: Masters Thesis
Full Text:: , Sirisha Adluri, Brian Owens, Chengang Xu, Chee Boon (Steven) Law, Patrick Birrer, Matt MacClary, SasiKu

A comparison of substrate noise coupling in heavily doped and lightly doped substrates for mixed-signal circuits

Creator:: Ayers, James S.
Abstract:: An analysis of substrate noise coupling in mixed-signal circuits has been performed in the TSMC 0.25 [mu]m lightly doped and heavily doped CMOS processes. Methods to minimize noise coupling in both the chip design and board design phases are presented along with techniques for accurate circuit simulation of noise coupling....
Resource Type:: Masters Thesis
Full Text:: , Brian Owens, Ajit Sharma, Bob Shreeve, Kyle Webb, Chenggang Xu, and all the other graduate students in

Predictive methodologies for substrate parasitic extraction and modeling in heavily doped CMOS substrates

Creator:: Sharma, Ajit
Abstract:: This thesis presents an automated methodology to calibrate the substrate profile for accurate prediction of substrate parasitics using Green's function based extractors. The technique requires fabrication of only a few test structures and results in an accurate three layered approximation of a heavily doped epitaxial silicon substrate. The obtained substrate...
Resource Type:: Masters Thesis
Full Text:: , Patrick Birrer, Brian Owens and Sirisha for all the help and cooperation on the substrate coupling

Analysis and modeling of substrate noise coupling for NMOS transistors in heavily doped substrates

Creator:: Hsu, Shu-ching
Abstract:: This thesis examines substrate noise coupling for NMOS transistors in heavily doped substrates. The study begins with the analysis of an NMOS transistor switching noise in a digital inverter at the device level. A resistive substrate network for the NMOS transistor is proposed and verified. Coupling between N+- P+ contacts...
Resource Type:: Masters Thesis
Full Text:: , Paul Hutchinson, Brian Owen, Ajit Sharma, and Robert Shreeve for all the help and cooperation on this

Silencer! : a tool for substrate noise coupling analysis

Creator:: Birrer, Patrick
Abstract:: This thesis presents Silencer!, a fully automated, schematic-driven tool for substrate noise coupling simulation and analysis. It has been integrated in the CADENCE DFII environment and seamlessly enables substrate coupling analysis in a standard mixed-signal design flow. Silencer! aids IC designers in the analysis of substrate noise coupling at different...
Resource Type:: Masters Thesis
Full Text:: Adluri, Brian Owens, and the rest of the Substrate Noise Coupling group for the cooperation in the

Comparison and impact of substrate noise due to clocked and clockless circuitry

Creator:: Le, Jim K.
Abstract:: Delay insensitive asynchronous circuitry provides significant advantages with respect to substrate noise due to localized switching. The differences between the substrate noise from NULL Convention Logic (NCL) and traditional Clocked Boolean Logic (CBL) are described and analyzed based on measured results. A test chip fabricated in the TSMC 0.25 um...
Resource Type:: Masters Thesis
Full Text:: −0.2 −0.1 0 0.1 0.2 Time (sec) M ag n it u d e (V ) 0 0.2 0.4 0.6 0.8 1 x 10 −6 −0.3

A 1-m W, 14-bit [sigma] [delta] A/D converter with 10-KHz conversion rate

Creator:: Gupta, Shivani
Resource Type:: Masters Thesis
Full Text:: the quantizer by a unity-gain element with an additive noise source, E(z), as shown in Fig. 2.2. E(z

ScholarsArchive@OSU

Simulation, measurement, and suppression of digital noise in mixed-signal integrated circuits

A DC-DC converter architecture for low-power, high-resistance thermoelectric generators for use in body-powered designs

Noise and Blocker Cancellation Techniques for Power and Area Efficient Wireless Receivers

A methodology for efficient substrate noise estimation from large scale digital circuits in mixed signal SoC's

A comparison of substrate noise coupling in heavily doped and lightly doped substrates for mixed-signal circuits

Predictive methodologies for substrate parasitic extraction and modeling in heavily doped CMOS substrates

Analysis and modeling of substrate noise coupling for NMOS transistors in heavily doped substrates

Silencer! : a tool for substrate noise coupling analysis

Comparison and impact of substrate noise due to clocked and clockless circuitry

A 1-m W, 14-bit [sigma] [delta] A/D converter with 10-KHz conversion rate

Limit your search

Academic Affiliation

Advisor

Commencement Year

Committee Member

Creator

Date

Decade

Degree Field

Degree Level

Degree Name

File Format

Language

License

Non-Academic Affiliation

Peer Reviewed

Resource Type

Rights Statement

Subject

Search Constraints

Search Results

Limit your search