Index Catalog // ScholarsArchive@OSU

A comparison of substrate noise coupling in heavily doped and lightly doped substrates for mixed-signal circuits

Creator:: Ayers, James S.
Abstract:: An analysis of substrate noise coupling in mixed-signal circuits has been performed in the TSMC 0.25 [mu]m lightly doped and heavily doped CMOS processes. Methods to minimize noise coupling in both the chip design and board design phases are presented along with techniques for accurate circuit simulation of noise coupling....
Resource Type:: Masters Thesis
Full Text:: along with techniques for accurate circuit simulation of noise coupling. Measurements from test chips

A substrate noise coupling model for lightly doped CMOS processes

Creator:: Sadate, Aline C.
Abstract:: This thesis presents a design-oriented model for lightly doped CMOS substrates. The model predicts the substrate noise coupling between noisy digital and sensitive analog blocks in the early stages of the design. The model scales with the size and separation of these blocks and it is validated with device simulations...
Resource Type:: Masters Thesis
Full Text:: used to predict noise coupling between an inverter and an amplifier, with both circuit simulations and

Analysis and modeling of substrate noise coupling for NMOS transistors in heavily doped substrates

Creator:: Hsu, Shu-ching
Abstract:: This thesis examines substrate noise coupling for NMOS transistors in heavily doped substrates. The study begins with the analysis of an NMOS transistor switching noise in a digital inverter at the device level. A resistive substrate network for the NMOS transistor is proposed and verified. Coupling between N+- P+ contacts...
Resource Type:: Masters Thesis
Full Text:: circuit simulations. This approach works well when supply noise is the dominant source of noise. The work

An efficient and accurate method of estimating substrate noise coupling in heavily doped substrates

Creator:: Arunachalam, Sasi Kumar S.
Abstract:: This thesis presents a Z-parameter based model to predict the substratenoise coupling between two contacts in a heavily doped substrate for frequenciesless than 2 GHz. The empirical model is scalable with contact size and spacingsbetween the contacts and model parameters can be readily extracted from simu-lated or measured data. The...
Resource Type:: Masters Thesis
Full Text:: : An Efficient and Accurate Method of Estimating Substrate Noise Coupling in Heavily Doped Substrates

A comparison of substrate noise coupling in lightly and heavily doped CMOS processes for 2.4 GHz LNA's

Creator:: Hazenboom, Duncan S.
Abstract:: Three types of low noise amplifiers operating at 2.4GHz were designed. They are the commonly used single-ended and differential amplifiers as well as a new quasi-differential amplifier. The substrate noise injected into these amplifiers is examined for both heavily and lightly doped CMOS substrates. For the single-ended amplifier the noise...
Resource Type:: Masters Thesis
Full Text:: is shown that the intermodulation noise is not reduced in a differential amplifier circuit. The

Simulation, measurement, and suppression of digital noise in mixed-signal integrated circuits

Creator:: Owens, Brian E.
Abstract:: Strategies for simulation and measurement of substrate noise have been analyzed using various digital and analog circuits fabricated in the TSMC 0.35um heavily doped CMOS process. The measurements validate a substrate noise coupling macromodel that has been used to obtain the simulation results. The simulations and measurements also substantiate the...
Resource Type:: Masters Thesis

Simulation and modeling of substrate noise generation from synchronous and asynchronous digital logic circuits

Creator:: Hanken, Christopher
Abstract:: Efficient methods for simulating the substrate noise generated by complex synchronous and asynchronous digital logic circuits are presented. By simulating digital logic at the gate level, and precharacterizing the gates, the substrate noise generation can be predicted and used in a transistor level simulation of the sensitive analog blocks. This...
Resource Type:: Masters Thesis
Full Text:: alignment is required for correct timing of substrate noise injections from the different circuit blocks

A methodology for efficient substrate noise estimation from large scale digital circuits in mixed signal SoC's

Creator:: Held, Martin A.
Abstract:: A methodology for rapid estimation of substrate noise generated by digital circuitry in mixed-signal circuits is presented. This methodology is incorporated into the Silencer! framework, and also provides for future improvements including pre-layout noise estimation. Measurements of a test chip fabricated in the TSMC o.25[mu]m heavily doped logic process validate...
Resource Type:: Masters Thesis
Full Text:: substrate currents may originate from impact ionization, capacitively coupled de- vices, or circuit noise

Silencer! : a tool for substrate noise coupling analysis

Creator:: Birrer, Patrick
Abstract:: This thesis presents Silencer!, a fully automated, schematic-driven tool for substrate noise coupling simulation and analysis. It has been integrated in the CADENCE DFII environment and seamlessly enables substrate coupling analysis in a standard mixed-signal design flow. Silencer! aids IC designers in the analysis of substrate noise coupling at different...
Resource Type:: Masters Thesis
Full Text:: the analysis may be the substrate noise at all the sensitive analog circuit locations in a chip

An enhanced swing differential Colpitts CMOS VCO for low-voltage operation

Creator:: Farahbakhshian, Farhad
Abstract:: An enhanced swing differential Colpitts VCO (ESDC-VCO) dramatically improves the swing of a Colpitts VCO by allowing the signal to swing below ground and above the supply voltage. Fabricated in a 1P8M 0.13 um CMOS process, the ESDC-VCO operates at 4.9GHz with a 0.475-V supply and consumes 2.7mW. The measured...
Resource Type:: Masters Thesis
Full Text:: and consumes 2.7mW. The measured phase noise is -136.2 dBc/Hz at a 3-MHz frequency offset. The ESDC

ScholarsArchive@OSU

A comparison of substrate noise coupling in heavily doped and lightly doped substrates for mixed-signal circuits

A substrate noise coupling model for lightly doped CMOS processes

Analysis and modeling of substrate noise coupling for NMOS transistors in heavily doped substrates

An efficient and accurate method of estimating substrate noise coupling in heavily doped substrates

A comparison of substrate noise coupling in lightly and heavily doped CMOS processes for 2.4 GHz LNA's

Simulation, measurement, and suppression of digital noise in mixed-signal integrated circuits

Simulation and modeling of substrate noise generation from synchronous and asynchronous digital logic circuits

A methodology for efficient substrate noise estimation from large scale digital circuits in mixed signal SoC's

Silencer! : a tool for substrate noise coupling analysis

An enhanced swing differential Colpitts CMOS VCO for low-voltage operation

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